Zobrazeno 1 - 10
of 20
pro vyhledávání: '"Tomofumi Yuki"'
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, In press, pp.1-15. ⟨10.1109/TCAD.2022.3201494⟩
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, In press, pp.1-15. ⟨10.1109/TCAD.2022.3201494⟩
Offloading compute-intensive kernels to hardware accelerators relies on the large degree of parallelism offered by these platforms. However, the effective bandwidth of the memory interface often causes a bottleneck, hindering the accelerator's effect
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::256421b54541789ae344b49e99bd2609
http://arxiv.org/abs/2202.05933
http://arxiv.org/abs/2202.05933
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783031045790
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8dfd2a94281eea6d4cc8651ee8af6f94
https://doi.org/10.1007/978-3-031-04580-6_30
https://doi.org/10.1007/978-3-031-04580-6_30
Publikováno v:
2021 Ninth International Symposium on Computing and Networking Workshops (CANDARW).
Publikováno v:
DATE 2020-23rd IEEE/ACM Design, Automation and Test in Europe
DATE 2020-23rd IEEE/ACM Design, Automation and Test in Europe, Mar 2020, Grenoble, France. pp.1-6
DATE
DATE 2020-23rd IEEE/ACM Design, Automation and Test in Europe, Mar 2020, Grenoble, France. pp.1-6
DATE
In this paper, we propose a method to improve the scalability of Word-Length Optimization (WLO) for large applications that use complex quality metrics such as Structural Similarity (SSIM). The input application is decomposed into smaller kernels to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::622d975c1bb67ca1c396ca27ab094749
https://hal.inria.fr/hal-02387232/document
https://hal.inria.fr/hal-02387232/document
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020, 39 (12), pp.4777-4790. ⟨10.1109/TCAD.2020.2981056⟩
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2020, 39 (12), pp.4777-4790. ⟨10.1109/TCAD.2020.2981056⟩
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020, 39 (12), pp.4777-4790. ⟨10.1109/TCAD.2020.2981056⟩
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2020, 39 (12), pp.4777-4790. ⟨10.1109/TCAD.2020.2981056⟩
International audience; In this article, we propose a technique for improving the efficiency of convolutional neural network hardware accelerators based on timing speculation (overclocking) and fault tolerance. We augment the accelerator with a light
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f5b5d82c35ba38c0e9999c2eb013c686
https://hal.inria.fr/hal-03094811/document
https://hal.inria.fr/hal-03094811/document
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2020, 39 (11), pp.4229-4239. ⟨10.1109/TCAD.2020.3012866⟩
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020, 39 (11), pp.4229-4239. ⟨10.1109/TCAD.2020.3012866⟩
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2020, 39 (11), pp.4229-4239. ⟨10.1109/TCAD.2020.3012866⟩
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020, 39 (11), pp.4229-4239. ⟨10.1109/TCAD.2020.3012866⟩
International audience; Loop pipelining is a key optimization in modern HLS tools for synthesizing efficient hardware datap-aths. Existing techniques for automatic loop pipelining are limited by static analysis that cannot precisely analyze loops wit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::192df954f1868bd92ca89fc8b7e032ff
https://hal.archives-ouvertes.fr/hal-02949516/document
https://hal.archives-ouvertes.fr/hal-02949516/document
Autor:
Mary Hall, Tomofumi Yuki, Catherine Olschanowsky, Eddie C. Davis, Anand Venkat, Maryam Mehri Dehnavi, Mahdi Soltan Mohammadi, Kazem Cheshmi, Michelle Mills Strout, Payal Nandy
Publikováno v:
PLDI 2019-40th ACM SIGPLAN Conference on Programming Language Design and Implementation
PLDI 2019-40th ACM SIGPLAN Conference on Programming Language Design and Implementation, Jun 2019, Phoenix, United States. pp.594-609, ⟨10.1145/3314221.3314646⟩
PLDI
PLDI 2019-40th ACM SIGPLAN Conference on Programming Language Design and Implementation, Jun 2019, Phoenix, United States. pp.594-609, ⟨10.1145/3314221.3314646⟩
PLDI
This paper presents a combined compile-time and runtime loop-carried dependence analysis of sparse matrix codes and evaluates its performance in the context of wavefront parallellism. Sparse computations incorporate indirect memory accesses such as x
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a6715ad047c28588e52e76476a047352
https://hal.inria.fr/hal-02396761
https://hal.inria.fr/hal-02396761
Autor:
Kazem Cheshmi, Mahdi Soltan Mohammadi, Anand Venkat, Tomofumi Yuki, Maryam Mehri Dehnavi, Michelle Mills Strout
Publikováno v:
Languages and Compilers for Parallel Computing ISBN: 9783030346263
LCPC
LCPC 2018-31st International Workshop on Languages and Compilers for Parallel Computing
LCPC 2018-31st International Workshop on Languages and Compilers for Parallel Computing, Oct 2018, Salt Lake City, United States
LCPC
LCPC 2018-31st International Workshop on Languages and Compilers for Parallel Computing
LCPC 2018-31st International Workshop on Languages and Compilers for Parallel Computing, Oct 2018, Salt Lake City, United States
Automatic parallelization is an approach where a compiler analyzes serial code and identifies computations that can be rewritten to leverage parallelism. Many data dependence analysis techniques have been developed to determine which loops in a code
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::380a30aa00eca68140afb0527e59162d
https://doi.org/10.1007/978-3-030-34627-0_7
https://doi.org/10.1007/978-3-030-34627-0_7
Publikováno v:
FPL-27th International Conference on Field Programmable Logic and Applications
FPL-27th International Conference on Field Programmable Logic and Applications, Sep 2017, Gand, Belgium. ⟨10.23919/FPL.2017.8056781⟩
FPL
FPL-27th International Conference on Field Programmable Logic and Applications, Sep 2017, Gand, Belgium. ⟨10.23919/FPL.2017.8056781⟩
FPL
International audience; Iterative stencils are kernels in various application domains such as numerical simulations and medical imaging, that merit FPGA acceleration. The best architecture depends on many factors such as the target platform, off-chip
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0265d5e8dc4355c3001f9cb42fe0ca02
https://hal.inria.fr/hal-01655590
https://hal.inria.fr/hal-01655590
Publikováno v:
2016 26th International Conference on Field Programmable Logic and Applications (FPL)
Field Programmable Logic and Applications (FPL), 2016 26th International Conference on
FPL 2016-26th International Conference on Field Programmable Logic and Applications
FPL 2016-26th International Conference on Field Programmable Logic and Applications, Aug 2016, Lausanne, Switzerland. IEEE, Field Programmable Logic and Applications (FPL), 2016 26th International Conference on, pp.1-4, 2016, 〈10.1109/FPL.2016.7577359〉
26th International Conference on Field-Programmable Logic and Applications
FPL 2016-26th International Conference on Field Programmable Logic and Applications, Aug 2016, Lausanne, Switzerland. pp.1-4, ⟨10.1109/FPL.2016.7577359⟩
FPL
Field Programmable Logic and Applications (FPL), 2016 26th International Conference on
FPL 2016-26th International Conference on Field Programmable Logic and Applications
FPL 2016-26th International Conference on Field Programmable Logic and Applications, Aug 2016, Lausanne, Switzerland. IEEE, Field Programmable Logic and Applications (FPL), 2016 26th International Conference on, pp.1-4, 2016, 〈10.1109/FPL.2016.7577359〉
26th International Conference on Field-Programmable Logic and Applications
FPL 2016-26th International Conference on Field Programmable Logic and Applications, Aug 2016, Lausanne, Switzerland. pp.1-4, ⟨10.1109/FPL.2016.7577359⟩
FPL
International audience; EURECA architectures have been proposed as an enhancement to existing FPGAs, to enable cycle-by-cycle reconfiguration. Applications with irregular data accesses, which previously cannot be efficiently supported in hardware, ca