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Autor:
Anita Karegar, Carson Henrion, Michael Dreesen, Michael K. Ciraula, Don R. Weiss, Russell Schreiber, John J. Wuu, Christopher George Helt, Ryan Freese, Bryan Schneller, Tommy Miles
Publikováno v:
ISSCC
High-performance multi-core processors require efficient multi-level cache hierarchies to meet high-bandwidth data requirements. Because level-3 (L3) cache is typically the largest cache on the die, the drive to lower cost places pressure on density,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a80f2408ca1589b48fb160e7e00c50ea
https://doi.org/10.1109/isscc.2011.5746309
https://doi.org/10.1109/isscc.2011.5746309
