Zobrazeno 1 - 10
of 89
pro vyhledávání: '"Tom J. Kazmierski"'
Autor:
Si Mon Kueh, Tom J. Kazmierski
Publikováno v:
IEEE Journal of Translational Engineering in Health and Medicine, Vol 6, Pp 1-9 (2018)
This paper presents results of using a simple bit-serial architecture as a method of designing an extremely low-power and low-cost neural network processor for epilepsy seizure prediction. The proposed concept is based on a novel bit-serial data proc
Externí odkaz:
https://doaj.org/article/b5a17a67e05d4d68bb347c9cc6e234af
Autor:
Charles Leech, Tom J. Kazmierski
Publikováno v:
Electronics, Vol 18, Iss 1, Pp 3-10 (2014)
This paper evaluates the present state of the art of energy-efficient embedded processor design techniques and demonstrates, how small, variable-architecture embedded processors may exploit a run-time minimal architectural synthesis technique to achi
Externí odkaz:
https://doaj.org/article/20863ee97db648ecbf2ed6f76912c2f3
Publikováno v:
Microelectronics Reliability. 93:16-21
Distributed arithmetic (DA) brings area and power benefits to digital designs relevant to the Internet-of-Things. Therefore, a new error resilient technique for DA computation is proposed to improve robustness against process, voltage, and temperatur
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9a1b6a9428b8f3553c26cd97ad210c9f
https://doi.org/10.1016/j.microrel.2018.12.007
https://doi.org/10.1016/j.microrel.2018.12.007
Publikováno v:
IEEE Journal of Solid-State Circuits. 54:550-559
Flip-flops (FFs) are essential building blocks of sequential digital circuits but typically occupy a substantial proportion of chip area and consume significant amounts of power. This paper proposes 18-transistor single-phase clocked (18TSPC), a new
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::93dce0ec81bca1f05fd3fa18f9b53312
https://doi.org/10.1109/jssc.2018.2875089
https://doi.org/10.1109/jssc.2018.2875089
Autor:
G. Domenech-Asensi, Tom J. Kazmierski
Publikováno v:
ISCAS
Repositorio Digital de la Universidad Politécnica de Cartagena
instname
Repositorio Digital de la Universidad Politécnica de Cartagena
instname
This paper presents a technique to parallelise a numeric integration solver on general purpose GPU. The technique is based on the combination of space state modeling with an explicit integration method based on the Adams-Bashforth second order formul
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c3c84a8a373ec193f52e50ba5992aea5
https://doi.org/10.1109/iscas45731.2020.9181157
https://doi.org/10.1109/iscas45731.2020.9181157
Autor:
Matthew Johns, Tom J. Kazmierski
Publikováno v:
FDL
This paper presents the first RISC-V vector processor design aimed at microcontrollers that uses the new RISC-V ‘V’ extension for vectors, part of the open-source RISC-V instruction set architecture (ISA). Being aimed at small embedded devices, i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c55e4c5fcb8297259805803762e4674d
https://doi.org/10.1109/fdl50818.2020.9232940
https://doi.org/10.1109/fdl50818.2020.9232940
Publikováno v:
Journal of Electronic Testing. 33:463-477
Low power fault tolerance design techniques trade reliability to reduce the area cost and the power overhead of integrated circuits by protecting only a subset of their workload or their most vulnerable parts. However, in the presence of faults not a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5e7085c084a4f2d18c823f9dc0562caf
https://doi.org/10.1007/s10836-017-5668-7
https://doi.org/10.1007/s10836-017-5668-7
Autor:
Tom J. Kazmierski, G. Domenech-Asensi
Publikováno v:
FDL
Repositorio Digital de la Universidad Politécnica de Cartagena
instname
Repositorio Digital de la Universidad Politécnica de Cartagena
instname
This paper describes an efficient numerical solution to speed up transient simulations of analog circuits on a many-core computer. The technique is based on an explicit integration method, parallelised on a multiprocessor architecture. Although the i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::24fdccd65b5fc82ccbe4623fc47b8c85
https://hdl.handle.net/10317/8331
https://hdl.handle.net/10317/8331
Autor:
G. Domenech-Asensi, Tom J. Kazmierski
Publikováno v:
Repositorio Digital de la Universidad Politécnica de Cartagena
instname
ISCAS
instname
ISCAS
This paper presents a technique to accelerate transient simulations of analog circuits using an explicit integration method parallelised on a many-core computer. Usual methods used by SPICE-type simulators are based on Newton–Raphson iterations, wh
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::dd392c221b2e88d42897d41d9224a201
https://hdl.handle.net/10317/10369
https://hdl.handle.net/10317/10369
Autor:
Tom J. Kazmierski, G. Domenech-Asensi
Publikováno v:
Repositorio Digital de la Universidad Politécnica de Cartagena
Fundación Universitaria San Pablo CEU (FUSPCEU)
DATE
Fundación Universitaria San Pablo CEU (FUSPCEU)
DATE
This work describes a high-speed simulation technique of analog circuits which is based on the use of statespace equations and an explicit integration method parallelised on a multiprocessor architecture. The integration step of such method is smalle
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::44a6f8b67ad83a28f5a13397dea03a75
http://hdl.handle.net/10317/8760
http://hdl.handle.net/10317/8760