Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Tokuzo Kiyohara"'
Autor:
Kozo Kimura, Takao Onoye, Tokuzo Kiyohara, Isao Shirakawa, Takayuki Sagishima, Hiroyuki Okuhata
Publikováno v:
The Journal of the Institute of Image Information and Television Engineers. 52:742-749
In this paper, we present a control method of data cache for a multithreaded processor and its evaluation. A multithreaded processor is effective for 3D-CG, however the increase of the working set size is unavoidable, and this limits the effectivenes
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::283a950706170dda766d8af9ad357a44
https://doi.org/10.3169/itej.52.742
https://doi.org/10.3169/itej.52.742
Autor:
Daniel M. Lavery, Richard E. Hank, William Y. Chen, Tokuzo Kiyohara, Grant Haab, John G. Holm, Wen-mei W. Hwu, Nancy J. Warter, Roland G. Ouellette, Scott Mahlke, Roger A. Bringmann, Pohua P. Chang
Publikováno v:
The Journal of Supercomputing. 7:229-248
A compiler for VLIW and superscalar processors must expose sufficient instruction-level parallelism (ILP) to effectively utilize the parallel hardware. However, ILP within basic blocks is extremely limited for control-intensive programs. We have deve
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ac22f133b7cec0d3052007f1f2a1cc8f
https://doi.org/10.1007/bf01205185
https://doi.org/10.1007/bf01205185
Autor:
Tokuzo Kiyohara, John C. Gyllenhaal
Publikováno v:
MICRO
Moderate size register files can limit the performance of loop unrolling on multiple issue processors. With current scheduling heuristics, a breadth-first scheduling of iterations occurs, increasing register pressure and generating excessive spill co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0b4379919445bfdb1c1417add941d634
https://doi.org/10.1145/144965.145802
https://doi.org/10.1145/144965.145802
Autor:
Richard E. Hank, Tokuzo Kiyohara, Sadun Anik, Roger A. Bringmann, William Y. Chen, Wen-mei W. Hwu, Scott Mahlke
Publikováno v:
ISCA
Code optimization and scheduling for superscalar and superpipelined processors often increase the register requirement of programs. For existing instruction sets with a small to moderate number of registers, this increased register requirement can be
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a4eda1a06c96918f5a33121bec9ab2e6
https://doi.org/10.1145/165123.165160
https://doi.org/10.1145/165123.165160
Autor:
Nancy J. Warter, Daniel M. Lavery, Richard E. Hank, John C. Gyllenhaal, Wen-mei W. Hwu, Scott Mahlke, William Y. Chen, Roger A. Bringmann, Tokuzo Kiyohara, Sadun Anik
Publikováno v:
Languages and Compilers for Parallel Computing ISBN: 9783540575023
LCPC
LCPC
Compilers for superscalar and VLIW processors must expose sufficient instruction-level parallelism in order to achieve high performance. Compiletime code transformations which expose instruction-level parallelism typically take into account the const
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e23eaa8ebfb8dfda01a3261dd2f88ca8
https://doi.org/10.1007/3-540-57502-2_38
https://doi.org/10.1007/3-540-57502-2_38
Autor:
Wen-Mei W. Hwu, Scott A. Mahlke, William Y. Chen, Pohua P. Chang, Nancy J. Warter, Roger A. Bringmann, Roland G. Ouellette, Richard E. Hank, Tokuzo Kiyohara, Grant E. Haab, John G. Holm, Daniel M. Lavery
Publikováno v:
Instruction-Level Parallelism ISBN: 9781461364047
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d7560170d36c9d9a84bca5fbc0a07687
https://doi.org/10.1007/978-1-4615-3200-2_7
https://doi.org/10.1007/978-1-4615-3200-2_7
Publikováno v:
ICS
By exploiting fine grain parallelism, superscalar processors can potentially increase the performance of future supercomputers. However, supercomputers typically have a long access delay to their first level memory which can severely restrict the per
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aa224d6d79ebe55fdee436cf9f444e09
https://doi.org/10.1145/143369.143394
https://doi.org/10.1145/143369.143394
Publikováno v:
TRON Project 1990 ISBN: 9784431681311
This paper is a report of the pipeline structure of a 32-bit microprocessor based on TRON specification with the on-chip floating-point unit (FPU). The FPU proposed here divides floating-point operations into two steps (each step performed during one
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4f5565f74d9ecca52dc2769247594e48
https://doi.org/10.1007/978-4-431-68129-8_14
https://doi.org/10.1007/978-4-431-68129-8_14
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