Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Tokuya Osawa"'
A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test
Autor:
Akira Yamazaki, Kazutami Arimoto, Masaru Haraguchi, Y. Okuno, Toshinori Morihara, Yoshikazu Morooka, Tokuya Osawa, Chikayoshi Morishima
Publikováno v:
IEICE Transactions on Electronics. :453-459
This paper describes new DDRx SDRAM interface architecture suitable for system-on-chip (SOC) implementation. Our test chip fabricated in a 90-nm CMOS process adopts three key schemes and achieves 960 Mb/s/pin operations with 32 bits width. One of new
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e29cca66e28fab5bc27c9b6449185e0e
https://doi.org/10.1587/transele.e92.c.453
https://doi.org/10.1587/transele.e92.c.453
Publikováno v:
Nishi Nihon Hifuka. 61:294-297
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c41b78b9c46fbdd465961dca53c757ed
https://doi.org/10.2336/nishinihonhifu.61.294
https://doi.org/10.2336/nishinihonhifu.61.294
Publikováno v:
IEEE Journal of Solid-State Circuits. 30:316-320
A novel memory cell circuit for multiport RAM on CMOS Sea-of-Gates (SOG) has been proposed. It contributes to the operation both at high speed and at low voltage. In addition, a fourfold read bit line technique is also proposed to reduce the access t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3c6c34a2edf2a6a95ba04bf2562aca5a
https://doi.org/10.1109/4.364448
https://doi.org/10.1109/4.364448
A Continuous-Adaptive DDR2 Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test
Autor:
Masaru Haraguchi, Akira Yamazaki, Tokuya Osawa, Toshinori Morihara, Y. Morooka, Kazutami Arimoto, Y. Okuno, Chikayoshi Morishima
Publikováno v:
ISSCC
An experimental chip for a 32b wide DDR2 SDRAM interface for SoC is fabricated in a 90nm CMOS process and achieves 960Mb/s/pin operation. Impedance-calibration circuits and flexible round-trip circuits in a continuous-adaptive DDR2 interface are used
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f3cf727021b9f3235bc69f1cb49370fd
https://doi.org/10.1109/isscc.2007.373508
https://doi.org/10.1109/isscc.2007.373508
Publikováno v:
Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.
A multi-port RAM generator for 0.5 /spl mu/m CMOS Sea-of-Gates (SOG) has been developed. 2-port or 3-port RAMs with flexible bit-word configurations are available. In order to operate either at a low supply voltage or at high speed, a novel memory ce
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::26203e1506355775a9961f9250f8806e
https://doi.org/10.1109/cicc.1994.379635
https://doi.org/10.1109/cicc.1994.379635
Conference
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.