Zobrazeno 1 - 10
of 51
pro vyhledávání: '"Tohru Furuyama"'
Autor:
Daisuke Hashimoto, Akihiro Nitayama, Daisaburo Takashima, Takeshi Hioka, Yoshiro Shimojo, Hidehiro Shiga, Yuki Yamada, Koji Yamakawa, Katsuhiko Hoya, Toyoki Taguchi, Shoichi Shimizu, Ryu Ogiwara, Hisaaki Nishimura, Tohru Ozaki, Yohji Watanabe, Shinichiro Shiratake, Sumiko Doumae, Iwao Kunishima, Tohru Furuyama, Tadashi Miyakawa, Hiroyuki Kanaya, Souichi Yamazaki, Shuso Fujii, Fumiyoshi Matsuoka, Yasushi Nagadomi, Ryo Fukuda, Ryosuke Takizawa, Yoshinori Kumura, Mitsumo Kawano, Susumu Shuto, Takeshi Hamamoto, Yoshihiro Minami, Kosuke Hatsuda
Publikováno v:
ISSCC
An 87.7 mm2 1.6 GB/s 128 Mb chain FeRAM with 130 nm 4-metal CMOS process is demonstrated. In addition to small bitline capacitance inherent to chain FeRAM architecture, three new FeRAM scaling techniques - octal bitline architecture, small parasitic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1fda70ed57de6c8e43a679a78faba8b0
https://doi.org/10.1109/jssc.2009.2034414
https://doi.org/10.1109/jssc.2009.2034414
Autor:
H. Furuhashi, Yohji Watanabe, Tohru Furuyama, Takeshi Hamamoto, Hiroomi Nakajima, Akihiro Nitayama, Tomoaki Shino, Fumiyoshi Matsuoka, Yoshihiro Minami, Ryo Fukuda, Tomoki Higashi, Takashi Ohsawa, Katsuyuki Fujita
Publikováno v:
IEEE Transactions on Electron Devices. 56:2302-2311
Physics of autonomous refresh is presented, which explains the mechanism of a spontaneous recovery of degraded binary states of the floating-body cell (FBC). Input current to the floating body and output current from the body balance to generate an u
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7a90a17948e6df6d7ac70923e8f5c011
https://doi.org/10.1109/ted.2009.2028396
https://doi.org/10.1109/ted.2009.2028396
Autor:
Tomoki Higashi, Kosuke Hatsuda, Tomoaki Shino, Takeshi Hamamoto, Tohru Furuyama, Yoshihiro Minami, Katsuyuki Fujita, Hiroomi Nakajima, Shuso Fujii, Shigeyoshi Watanabe, Takashi Ohsawa, Mutsuo Morikado, K. Inoh
Publikováno v:
IEEE Journal of Solid-State Circuits. 41:135-145
A 128-Mb SOI DRAM has been developed featuring the floating body cell (FBC). To keep the cell data state from being degraded by the word-line (WL) disturb due to the charge pumping and to reduce the refresh busy rate, a sense amplifier (S/A) is arran
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7bdf900e64f47739a240c54a25a8b70f
https://doi.org/10.1109/jssc.0051.859018
https://doi.org/10.1109/jssc.0051.859018
Autor:
Yohji Watanabe, Hideho Arakida, N. Machida, Osamu Yamagishi, T. Samata, Tsuyoshi Nishikawa, Tohru Furuyama, M. Takahashi, Shigenobu Minami, Toshihide Fujiyoshi, T. Terazawa, K. Ohmori, J. Shirakura, Asano Atsushi, M. Hamada, Tadahiro Kuroda, Toshinari Takayanagi, Hideaki Yamamoto, Hiroshi Nakamura
Publikováno v:
IEEE Journal of Solid-State Circuits. 35:1713-1721
A 240-mW single-chip MPEG-4 videophone LSI with a 16-Mb embedded DRAM is fabricated utilizing a 0.25-/spl mu/m CMOS triple-well quad-metal technology. The videophone LSI is applied to the 3GPP 3G-324M video-telephony standard for IMT-2000, and implem
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::039c25faf481327101f30fc320ee5d28
https://doi.org/10.1109/4.881219
https://doi.org/10.1109/4.881219
Autor:
K. Matsuda, T. Fujita, Takayasu Sakurai, Tohru Furuyama, Yohji Watanabe, T. Maeda, A. Chiba, Kojiro Suzuki, Shinji Mita, Tadahiro Kuroda, F. Yamane, F. Sano
Publikováno v:
IEEE Journal of Solid-State Circuits. 33:454-462
This paper describes a variable supply-voltage (VS) scheme. From an external supply, the VS scheme automatically generates minimum internal supply voltages by feedback control of a buck converter, a speed detector, and a timing controller so that the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d49c71231b8ba22bb4aaaec0570a7157
https://doi.org/10.1109/4.661211
https://doi.org/10.1109/4.661211
Autor:
Tadahiro Kuroda, M. Hamada, T. Terazawa, F. Sano, H. Momose, Yoshiro Tsuboi, M. Takahashi, Kojiro Suzuki, A. Chiba, T. Fujita, Tohru Furuyama, Kimiyoshi Usami, Mutsunori Igarashi, Masahiro Kanazawa, Tsuyoshi Nishikawa, Fumitoshi Hatori, Takashi Ishikawa, Shinji Mita, Yohji Watanabe, Hideho Arakida
Publikováno v:
IEEE Journal of Solid-State Circuits. 33:1772-1780
A 60-mW MPEG4 video codec has been developed for mobile multimedia applications. This codec supports both the H.263 ITU-T recommendation and the simple profile of MPEG4 committee draft version 1 released in November 1997. It is composed of a 16-bit r
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b878d325f09d4a1e3f5fb4662a5428db
https://doi.org/10.1109/4.726575
https://doi.org/10.1109/4.726575
Autor:
M. Hannah, M. Nagy, Y. Kawashima, H. Shinya, M. Iwase, Junpei Kumagai, M. Ohgata, P. Hansen, Tohru Furuyama, Takeshi Yoshida, Kenji Numata, Tomoaki Yabe, M. Enkaku, N. Yanagiya, Ryo Haga, Seiji Kaki, M. Rungsea, M. Sakurai, Anan Nagarajan, Kazuyuki Sato, Shinji Miyano, M. Shiochi, M. Wada
Publikováno v:
IEEE Journal of Solid-State Circuits. 30:1281-1285
To realize high data-transfer rate in random access, several kinds of DRAMs with on-chip cache memory have been proposed. These DRAMs rely on locality of access to achieve the highest speed. However, in some graphic applications where sufficient loca
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::515975b80090ae1e0294ececa832f02e
https://doi.org/10.1109/4.475717
https://doi.org/10.1109/4.475717
Autor:
Mark Horowitz, Satoru Takase, Matthew Murdy Griffin, Victor E. Lee, D. Stark, John B. Dillon, Thomas H. Lee, Shigeo Ohshima, Natsuki Kushiyama, Tohru Furuyama, A. Chan, R.M. Barth, H. Noji, Kiyofumi Sakurai, James A. Gasbarro
Publikováno v:
IEEE Journal of Solid-State Circuits. 28:490-498
A 512-kb*9 DRAM with a 500-Mbyte/s data transfer rate was developed. This high data rate was achieved by designing a DRAM core with a very high internal column bandwidth, and coupling this core with a block-oriented, small-swing, synchronous interfac
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::98ca8a8d722c6af70620c260262ed620
https://doi.org/10.1109/4.210033
https://doi.org/10.1109/4.210033
Publikováno v:
IEEE Journal of Solid-State Circuits. 26:479-483
A 12 MHz data-cycle 4 Mb DRAM (dynamic RAM) with pipeline operation was designed and fabricated using 0.8 mu m twin-tub CMOS technology. The pipeline DRAM outputs data corresponding to addresses that were accepted in the previous inverted random acce
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::39dc4559bc4e5706438be680352ae8d6
https://doi.org/10.1109/4.75042
https://doi.org/10.1109/4.75042