Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Tobias Mono"'
Autor:
U. Zimmermann, Tobias Mono, T. Tran, D. Temmler, F. Ludwig, Arnd Scholz, J. Hartwich, G. Wedler, Hans-Peter Moll, Andrew Graham, W. Muller, K. Schupke, S. Slesazek, Lars Heineck, Inho Park
Publikováno v:
2007 IEEE Symposium on VLSI Technology.
We report an enabling technology for 40 nm trench DRAM and beyond. The 3-dimensional array transistor is formed self-aligned (SA) to the deep trench (DT) capacitor; and the single-sided strap contact (SC) connecting the array transistor to the trench
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5188836875fb80628e8ada8533f9d3ff
https://doi.org/10.1109/vlsit.2007.4339687
https://doi.org/10.1109/vlsit.2007.4339687
Autor:
Markus Veldkamp, Jens Uwe Bruch, Katrin Palitzsch, Uwe Schroeder, Dieter Nees, Ralf Schuster, Wolfram Koestler, Sirko Kramp, Tobias Mono
Publikováno v:
SPIE Proceedings.
Generally, the potential impact of systematical overlay errors on 300mm wafers is much larger than on 200mm wafers. Process problems which are merely identified as minor edge yield detractors on 200mm wafers, can evolve as major roadblocks for 300mm
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9dd8839418ee070d30d58f87b02062bb
https://doi.org/10.1117/12.485019
https://doi.org/10.1117/12.485019
Autor:
E. Hsiung, Terry A. Spooner, G. Brase, Erdem Kaltalioglu, F. Grellner, Mark Hoinkis, B. von Ehrenwall, D. Warner, Klaus Schruefer, T. Schiml, L. Burrell, Robert C. Wong, C. Wang, Thomas Schafbauer, A. Von Ehrenwall, Tobias Mono, P. Kim, G. Knoblinger, Fernando Guarin, K.C. Chen, Petra Felsner, Alan J. Leslie, Uwe Schroeder, S. Biesemans, E. Demm, Andy Cowley, J. Gill, L.K. Han, S. Kulkarni, P. Leung
Publikováno v:
2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).
We describe an advanced 0.13 /spl mu/m CMOS technology platform optimized for density, performance, low power and analog/mixed signal applications. Up to 8 levels of copper interconnect with the industry's first true low-k dielectric (SiLK, k=2.7) (G
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1a52140b062f05c7d625e27c2facbcf4
https://doi.org/10.1109/vlsit.2001.934969
https://doi.org/10.1109/vlsit.2001.934969
Autor:
Uwe Schroeder, Tobias Mono
Publikováno v:
SPIE Proceedings.
In this paper we demonstrate a method of correcting optical proximity effects, which is specifically tailored for logic applications. Since the lithographic process window for printing logic features is predominantly determined by isolated lines, it
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::df9b2ca3350d5273d14c1dfab8f92419
https://doi.org/10.1117/12.388933
https://doi.org/10.1117/12.388933
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