Zobrazeno 1 - 10
of 24
pro vyhledávání: '"Ting-Pu Tai"'
Autor:
Ting-Pu Tai
Publikováno v:
2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9473b5c99d16fc8fb9b5521752bf7614
https://doi.org/10.1109/vlsi-tsa/vlsi-dat57221.2023.10134137
https://doi.org/10.1109/vlsi-tsa/vlsi-dat57221.2023.10134137
Autor:
Khader Abdel-Hafez, Michael Dsouza, Likith Kumar Manchukonda, Elddie Tsai, Karthikeyan Natarajan, Ting-Pu Tai, Wenhao Hsueh, Smith Lai
Publikováno v:
2022 IEEE International Test Conference (ITC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::99f97ad9bc701ac87a9687e573fb3ea7
https://doi.org/10.1109/itc50671.2022.00041
https://doi.org/10.1109/itc50671.2022.00041
Autor:
Ting-Pu Tai, Steve Pateras
Publikováno v:
VLSI-DAT
Meeting the quality and reliability requirements of the ISO 26262 and other automotive electronics standards will only become more difficult as device sizes and complexities continue to grow. New advanced test technologies such as cell-aware ATPG, hy
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0321df8e6a40e9dc04f8babff342aad8
https://doi.org/10.1109/vlsi-dat.2017.7939655
https://doi.org/10.1109/vlsi-dat.2017.7939655
Publikováno v:
ECS Transactions. 44:1029-1035
The time to market of a digital device includes first silicon debug, yield ramp and mature yield improvement. Manufacturing test failures caused by defects during mature yield state are usually hard to characterize for advanced technologies and resem
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1eede660ca8c0fb32e8023f678a9419b
https://doi.org/10.1149/1.3694425
https://doi.org/10.1149/1.3694425
Autor:
Yi-Jung Chang, Man-Ting Pang, Mike Brennan, Albert Man, Martin Keim, Geir Eide, Brady Benware, Ting-Pu Tai
Publikováno v:
EDFA Technical Articles. 12:12-18
This case study compares the FA success rate and turn-around time of traditional logic-only and true layout-aware scan diagnosis. It discusses the basic process flow, identifies key success factors, and evaluates physical FA and diagnostic test resul
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ae4fdd803f2673e5989ef9a0decb9de2
https://doi.org/10.31399/asm.edfa.2010-2.p012
https://doi.org/10.31399/asm.edfa.2010-2.p012
Publikováno v:
VLSI-DAT
The semiconductor industry is encountering an increasing number of front-end-of-line defects in the advanced FinFET technology nodes due to extremely small feature size and complex manufacturing processes required for FinFET transistors. Traditional
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::12e97e8a8d613045a075951a761fbd8d
https://doi.org/10.1109/vlsi-dat.2015.7114547
https://doi.org/10.1109/vlsi-dat.2015.7114547
Autor:
Ting-Pu Tai
Publikováno v:
2015 China Semiconductor Technology International Conference.
Traditionally, the foundry is responsible for yield enhancement when excursion yield loss occurs. Sometimes the cycle time to fix the problems is too long and can be unpredictable due to a lack of design details and process uncertainty on the foundry
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6fbfa89983bff4f79bae35fec83b8cd3
https://doi.org/10.1109/cstic.2015.7153450
https://doi.org/10.1109/cstic.2015.7153450
Autor:
Yu Hu, Wei-Pin Changchien, Sandeep C. Eruvathi, Ruifeng Guo, S. Pan, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Jing Ye, Yu Huang, Charles C. C. Liu, Ji-Jan Chen, Daw-Ming Lee, Kartik K. Kumara, Wu-Tung Cheng
Publikováno v:
ITC
Without appropriate stitching of scan chains, even with good diagnosis algorithm and diagnostic pattern generation, the chain diagnostic resolution may still be bad. In this paper, we propose a novel pattern-independent diagnosis and layout aware (DL
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5fa2ef08b254145b5939c9f30c4f8919
https://doi.org/10.1109/test.2013.6651929
https://doi.org/10.1109/test.2013.6651929
Publikováno v:
International Symposium for Testing and Failure Analysis.
If a signal on clock tree is slower than expected due to either a design error or a manufacturing defect, it may cause complicated fault behaviors during scan-based testing. It makes the diagnosis of such defect especially difficult if the defective
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f24cc96a6039e3acc615d20ff376641f
https://doi.org/10.31399/asm.cp.istfa2011p0103
https://doi.org/10.31399/asm.cp.istfa2011p0103
Autor:
Manish Sharma, Sergej Schwarz, Yuan-Shih Chen, Feng-Ming Kuo, Michael Brennan, James Yeh, Ting-Pu Tai, Kathy Yang, Alan Ma, Juergen Schmerberg, Cheng-Yiing Chuang
Publikováno v:
International Symposium for Testing and Failure Analysis.
Logic diagnosis analyzes scan test failures and produces a list of potential defect locations and types. This information is often used as a starting point for a detailed physical failure analysis (PFA) process that locates the actual physical defect
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4ee20a340c41ab1fc0efee55afa10428
https://doi.org/10.31399/asm.cp.istfa2011p0086
https://doi.org/10.31399/asm.cp.istfa2011p0086