Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Ting-Kuei Kuan"'
Autor:
Ting-Kuei Kuan, 管挺貴
103
Since 1930s, phase-locked loops (PLLs) have been widely employed in radio, telecommunications, computers and other electronic devices. Specifically, they can be used to generate well-timed clocks for a variety of applications such as clock a
Since 1930s, phase-locked loops (PLLs) have been widely employed in radio, telecommunications, computers and other electronic devices. Specifically, they can be used to generate well-timed clocks for a variety of applications such as clock a
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/36408606089394812217
Autor:
Ting-Kuei Kuan, Shen-Iuan Liu
Publikováno v:
IEEE Journal of Solid-State Circuits. 51:821-831
This paper presents a digital bang–bang phase-locked loop (DBPLL) that employs automatic loop gain control and loop latency reduction techniques to enhance the jitter performance. Due to noise filtering properties, a DBPLL has an optimal loop gain
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::39b89f3501da81fd44c6c2dd6e0f299b
https://doi.org/10.1109/jssc.2016.2519391
https://doi.org/10.1109/jssc.2016.2519391
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 62:1033-1037
A subharmonically injection-locked all-digital phase-locked loop (ADPLL) without a main divider is presented. It achieves not only low power but also low phase noise over the process, voltage, and temperature (PVT) variations. This ADPLL uses only a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ad238e058e0f259a6d212d77e89781a9
https://doi.org/10.1109/tcsii.2015.2455292
https://doi.org/10.1109/tcsii.2015.2455292
Autor:
Shen-Iuan Liu, Ting-Kuei Kuan
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 62:1873-1882
This paper presents a loop gain optimization technique for integer- $N$ digital phase-locked loops with a time-to-digital converter. Due to noise filtering properties, a phase-locked loop has an optimal loop gain which gives rise to the best jitter p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::319dab94807d7d14f88526dbce83a748
https://doi.org/10.1109/tcsi.2015.2423793
https://doi.org/10.1109/tcsi.2015.2423793
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 62:548-552
A subharmonically injection-locked phase-locked loop (SIPLL) using a pulsewidth-calibrated loop is presented. The injection timing and the pulsewidth of the injected pulse are calibrated to tolerate the process variations. This SIPLL is fabricated in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4f8e5d10f740f072ec9b223604a9e7f8
https://doi.org/10.1109/tcsii.2015.2407753
https://doi.org/10.1109/tcsii.2015.2407753
Publikováno v:
A-SSCC
A digital multiplying delay-locked loop (DMDLL) is presented to reduce the low-frequency phase noise and lower the power. The main divider is also turned off to reduce the power. The digitally-controlled oscillator uses the switched biasing technique
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9a5a131005d55f7bb512aacea445f8e6
https://doi.org/10.1109/asscc.2016.7844145
https://doi.org/10.1109/asscc.2016.7844145
Autor:
Shen-Iuan Liu, Ting-Kuei Kuan
Publikováno v:
VLSIC
This paper presents a digital bang-bang phase-locked loop that employs automatic loop gain control and loop latency reduction techniques to enhance the jitter performance. The chip is fabricated in a 40nm CMOS process. This bang-bang phase-locked loo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7020b3a312b76fbd44c69cf877924fd8
https://doi.org/10.1109/vlsic.2015.7231354
https://doi.org/10.1109/vlsic.2015.7231354
Publikováno v:
A-SSCC
A small-area energy-efficient true random number generator (TRNG) is presented. This TRNG introduces a jitter signal generator to realize the noise pre-amplification, and utilizes a metastable latch to resolve the jitter edges. Moreover, to tolerate
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fdeb533ffbf9fb675fdbb9a620e5d25c
https://doi.org/10.1109/asscc.2014.7008853
https://doi.org/10.1109/asscc.2014.7008853