Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Timothy Diemoz"'
Autor:
David Hogenmiller, Pierce Chuang, Saiful Islam, Ricardo Escobar, Daniel Lewis, Joshua Friedrich, Donald W. Plass, Rahul M. Rao, Pawel Owczarczyk, Paul H. Muench, Eric Fluhr, Michael A. Sperling, Juergen Pille, Vinod Ramadurai, Jose Angel Paredes, Michael Stephen Floyd, Christopher Gonzalez, Phillip J. Restle, Timothy Diemoz, Ryan Nett, Christos Vezyrtis, Ryan Kruse, Daniel M. Dreps
Publikováno v:
IEEE Journal of Solid-State Circuits. 53:91-101
The POWER9TM family of chips is fabricated in 14-nm silicon-on-insulator finFET technology using 17 levels of copper interconnect. The 695-mm2 24-core microprocessor features a new core based on an execution slice microarchitecture. The chip contains
Autor:
John F. Bulzacchelli, Michael A. Sperling, Zeynep Toprak-Deniz, Timothy Diemoz, Perez Miguel E
Publikováno v:
CICC
A distributed network of low-dropout (LDO) microregulators (uREGs) senses and corrects the voltages at multiple points on a power supply grid in a multi-core microprocessor to reduce errors due to IR drops. A voltage regulator controller (VREGC) comp
Autor:
Yong Kim, Keith A. Jenkins, David W. Siljenberg, Steve Baumgartner, Jason D. Hibbeler, Kevin Stawiasz, Daniel M. Dreps, Zeynep Toprak-Deniz, Donald W. Plass, James D. Warnock, Michael A. Sperling, Joshua Friedrich, David William Boerstler, Phillip J. Restle, Gregory Scott Still, R. P. Robertazzi, George English, Paul H. Muench, Eric Fluhr, Juergen Pille, Jose Angel Paredes, Anne E. Gattiker, John F. Bulzacchelli, David Shan, Ryan Nett, Glen A. Wiedemeier, Victor Zyuban, Tilman Gloekler, Christopher Gonzalez, Timothy Diemoz
Publikováno v:
IEEE Journal of Solid-State Circuits. 50:10-23
POWER8™ is a 12-core processor fabricated in IBM's 22 nm SOI technology with core and cache improvements driven by big data applications, providing 2.5× socket performance over POWER7+™. Core throughput is supported by 7.6 Tb/s of off-chip I/O b
Autor:
Pawel Owczarczyk, Michael A. Sperling, Pierce Chuang, Phillip J. Restle, Joshua Friedrich, Christos Vezyrtzis, Timothy Diemoz, Paul H. Muench, Eric Fluhr, Michael Stephen Floyd
Publikováno v:
ISSCC
Increasing transistor counts in modern processors can create instantaneous changes in current, driving nanosecond-speed supply voltage (V DD ) droops that require extra guardband for correct product operation. The POWER9 processor uses an adaptive cl
Autor:
Ryan Kruse, George English, Zeynep Toprak-Deniz, David T. Hui, Paul H. Muench, R. P. Robertazzi, Kevin Stawiasz, Seongwon Kim, David William Boerstler, Michael A. Sperling, Gregory Scott Still, Timothy Diemoz, Tilman Gloekler, Joshua Friedrich, John F. Bulzacchelli
Publikováno v:
ISSCC
Integrated voltage regulator modules (iVRMs) [1] provide a cost-effective path to realizing per-core dynamic voltage and frequency scaling (DVFS), which can be used to optimize the performance of a power-constrained multi-core processor. This paper p
Autor:
Daniel Friedman, Keith A. Jenkins, Kevin Stawiasz, Jose A. Tierno, Timothy Diemoz, Gaurav Rao, Paul H. Muench, David T. Hui, Ann Chen, George William Smith, Anthony E. Ciesla, George English, Michael A. Sperling, Alexander V. Rylyakov
Publikováno v:
2010 Symposium on VLSI Circuits.
A per-core clock generator for the eight-core POWER7™ processor is implemented with a digital PLL. This frequency generator is capable of smooth, controlled frequency slewing, minimizing the impact of di/dt. Frequency can be dynamically adjusted wh
Autor:
John Sylvestri, George William Smith, Timothy Diemoz, Seongwon Kim, Paul H. Muench, Hector Saenz, Norman Karl James, Peilin Song, Franco Stellari, S. Ippolito
Publikováno v:
ITC
As design complexity increases and process technologies shrink, high resolution and quick turnaround diagnostics are always in high demand. This is especially important for the development of high performance microprocessors, where not only the gross
Autor:
Richard F. Rizzolo, Steven Bennett Wilson, Timothy Diemoz, John P. Pennings, Tami Vogel, Franco Stellari, Alan J. Weger, Peilin Song
Publikováno v:
ITC
In this paper, the paper discuss a diagnostics methodology based on the combined use of advanced chip cooling technology and high-resolution time-integrated images of the light emission due to off-state leakage current (LEOSLC). The methodology was s