Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Tianyue Lu"'
Publikováno v:
BenchCouncil Transactions on Benchmarks, Standards and Evaluations, Vol 2, Iss 2, Pp 100061- (2022)
In future data centers, applications will make heavy use of far memory (including disaggregated memory pools and NVM). The access latency of far memory is more widely distributed than that of local memory accesses. This makes the efficiency of tradit
Externí odkaz:
https://doaj.org/article/7856828864e4458da39c39f823ad4ec5
Autor:
LUMING WANG, XU ZHANG, SONGYUE WANG, ZHUOLUN JIANG, TIANYUE LU, MINGYU CHEN, SIWEI LUO, KEJI HUANG
Publikováno v:
ACM Transactions on Architecture & Code Optimization; Sep2024, Vol. 21 Issue 3, p1-28, 28p
Autor:
Haifeng Li, Ke Liu, Ting Liang, Zuojun Li, Tianyue Lu, Hui Yuan, Yinben Xia, Yungang Bao, Mingyu Chen, Yizhou Shan
Publikováno v:
2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::65a03f59d9f2684d2e1fa1a830687686
https://doi.org/10.1109/hpca56546.2023.10070986
https://doi.org/10.1109/hpca56546.2023.10070986
Publikováno v:
2022 International Conference on Field-Programmable Technology (ICFPT).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2e344cfdfd8416dae1264dedf7578c2f
https://doi.org/10.1109/icfpt56656.2022.9974189
https://doi.org/10.1109/icfpt56656.2022.9974189
Publikováno v:
ICPADS
On modern multi-core machines, page coloring has been used to alleviate the competition at Last Level Cache (LLC). However, the latest development of CPU architecture has brought new issues to page coloring. Firstly, in the case of three-level cache,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d20fdca6e336252c6ede43abd404ff73
https://doi.org/10.1109/icpads47876.2019.00051
https://doi.org/10.1109/icpads47876.2019.00051
Publikováno v:
HPCC/SmartCity/DSS
To meet the memory capacity requirement of big-data applications, a promising architecture is that NVM (Non-Volatile Memory) is used as main memory and external DRAM (off-chip) is used as cache. Compared to LLC versus DRAM (referred to as L-DRAM), ex
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::92e15c2c57e0e14d4497881dad208e57
https://doi.org/10.1109/hpcc/smartcity/dss.2019.00064
https://doi.org/10.1109/hpcc/smartcity/dss.2019.00064
Autor:
Tianyue Lu, Wee-Yeap Lau
Publikováno v:
The Chinese Management Book-of-Readings Series ISBN: 9789811328404
This study examines the linkages between Chinese shadow banking, monetary policy and macroeconomic variables. This analytical work is original as compared to most of the studies which are descriptive and theoretical in nature. Based on the survey of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f72aeed4196ce1dbcdef3c2b1ba4d200
https://doi.org/10.1007/978-981-13-2841-1_10
https://doi.org/10.1007/978-981-13-2841-1_10
Publikováno v:
ISPRS International Journal of Geo-Information, Vol 13, Iss 6, p 186 (2024)
The construction of new towns is one of the main measures to evacuate urban populations and promote regional coordination and urban–rural integration in China. Mining the spatio-temporal pattern of new town hot spots based on multivariate data and
Externí odkaz:
https://doaj.org/article/5f56c06fdb53484495ed7327092f108f
Publikováno v:
ISPA/IUCC
Non-Volatile Memory (NVM) is better than traditional DRAM with respect to energy efficiency and larger capacity, so NVM has begun to be used as main memory. NVM provides data persistence that data written into NVM will not be lost during unexpected s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a5670ef451ce7995485ea66a248c96b9
https://doi.org/10.1109/ispa/iucc.2017.00071
https://doi.org/10.1109/ispa/iucc.2017.00071
Publikováno v:
ICCD
Emerging Non-Volatile Memory (NVM) provides both larger memory capacity and higher energy efficiency, but has much longer access latency than traditional DRAM, thus DRAM can be used as an efficient cache to hide the long latency of Non-Volatile Main
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6bf10cd4349c08c7897fac6765dca734
https://doi.org/10.1109/iccd.2017.19
https://doi.org/10.1109/iccd.2017.19