Zobrazeno 1 - 10
of 24
pro vyhledávání: '"Tian Chun Ye"'
Autor:
Ying-Fei Wang, Qing-Chun Zhang, Ping Li, Xiao-Jing Su, Li-Song Dong, Rui Chen, Li-Bin Zhang, Tian-Yang Gai, Ya-Juan Su, Ya-Yi Wei, Tian Chun Ye
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 9, Pp 6-9 (2021)
For the first time, this research addresses the notable layout proximity effects induced by stress memorization technique in planer high-k/Metal gate NMOS device systematically, including width effect, different shallow trench spacing effect, and len
Externí odkaz:
https://doaj.org/article/3269a09e61a045ebb74841b3612bc1ff
Autor:
Yajuan Su, Qing-Chun Zhang, Ying-Fei Wang, Rui Chen, Tianyang Gai, Libin Zhang, Ping Li, Xiaojing Su, Lisong Dong, Yayi Wei, Tian Chun Ye
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 9, Pp 6-9 (2021)
For the first time, this research addresses the notable layout proximity effects induced by stress memorization technique in planer high-k/Metal gate NMOS device systematically, including width effect, different shallow trench spacing effect, and len
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::be32dc7e74a79960d46c8021a0621ec0
https://doi.org/10.1109/jeds.2020.3032957
https://doi.org/10.1109/jeds.2020.3032957
Publikováno v:
Progress In Electromagnetics Research M. 85:125-134
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::46c8d8629d298fec2fc2e885277926e8
https://doi.org/10.2528/pierm19071803
https://doi.org/10.2528/pierm19071803
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25:1919-1929
This paper presents the design and implementation of memory-based fast Fourier transform (FFT) processors with generalized efficient, conflict-free address schemes. We unified the conflict-free address schemes of three different FFT lengths, includin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::786769c8c3f06a5a907f1d450106129d
https://doi.org/10.1109/tvlsi.2017.2666820
https://doi.org/10.1109/tvlsi.2017.2666820
Publikováno v:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :592-601
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::167280d7b83b9dd0390da3512cba45ff
https://doi.org/10.1587/transfun.e100.a.592
https://doi.org/10.1587/transfun.e100.a.592
Publikováno v:
Progress in Electromagnetics Research M; 2019, Vol. 85, p125-134, 13p
Publikováno v:
Advanced Materials Research. 629:139-144
Fermi level pinning (FLP) and dipole formation in TiN/HfO2/SiO2/Si stacks are investigated. The magnitude of FLP at TiN/HfO2 interface is estimated to be ~0 V based on dipole theory using concepts of interfacial gap states and charge neutrality level
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::457bccde368254f69bee17e72ffaf1d1
https://doi.org/10.4028/www.scientific.net/amr.629.139
https://doi.org/10.4028/www.scientific.net/amr.629.139
Publikováno v:
Physica B: Condensed Matter. 407:2943-2946
The surface blistering phenomenon produced in H-implanted Ge by a series of low temperature annealing processes was investigated. The kinetic plot of the onset of blistering contains a break point that separates the straight-line plot into two parts,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5cb30d62329f6411db48edf11ea50dac
https://doi.org/10.1016/j.physb.2011.08.109
https://doi.org/10.1016/j.physb.2011.08.109
Publikováno v:
ECS Transactions. 41:355-364
The annealing blistering after hydrogen implantation is a fundamental to achieve GeOI (germanium-on-insulator) by the well-known Smart-cut process. The impacts of H implantation dose and energy on the annealing kinetic plots are studied. The experime
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7bcbbdda2ab25af97cefe91e338b146a
https://doi.org/10.1149/1.3633316
https://doi.org/10.1149/1.3633316
Publikováno v:
2012 3rd IEEE International Workshop on Low Temperature Bonding for 3D Integration.
Low temperature wafer bonding for InP/Si and InP/SiO 2 was studied. Scanning acoustic microscopy (SAM) has to be used for characterizing the bonding interface to determine if there are micro-voids ( 2 bonding. The micro-voids also appear in the wafer
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::092a1ff51d86a213bfaddfd2e08c4c47
https://doi.org/10.1109/ltb-3d.2012.6238054
https://doi.org/10.1109/ltb-3d.2012.6238054