Zobrazeno 1 - 10
of 15
pro vyhledávání: '"Thuy Tran-Quinn"'
Autor:
Souvick Mitra, You Li, Robert Gauthier, Gebreselasie Ephrem G, Thuy Tran-quinn, Koushik Ramachandran
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 16:497-503
A set of design of experiments matrix was created to evaluate the possibilities of electrostatic-discharge (ESD) failures during the complex 3-D integration process as a function of the ESD protection level. A detailed set of pass/fail criteria based
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b74a174edba0e001563e6f799647b249
https://doi.org/10.1109/tdmr.2016.2627522
https://doi.org/10.1109/tdmr.2016.2627522
Publikováno v:
IRPS
Stacking of chips vertically will reduce the interconnection resistance and as a result enhance data communication between chips. Memory chip to logic chip integration requires close proximity to improve the performance and is an alternate to SOC typ
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::992510202272b9e4038c41b86fab1209
https://doi.org/10.1109/irps.2019.8720515
https://doi.org/10.1109/irps.2019.8720515
Autor:
Lloyd Burrell, S. Cimino, Patrick Justison, Thuy Tran-Quinn, C.S. Premachandran, Seungman Choi
Publikováno v:
IRPS
Stacking of chips vertically will reduce the interconnection resistance between the chips and also enhance data communication between them. Memory chip to logic chip integration requires close proximity to improve the performance and is an alternate
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::085f271ce78a19e53f6d9be112017be9
https://doi.org/10.1109/irps.2018.8353609
https://doi.org/10.1109/irps.2018.8353609
Autor:
Daniel Berger, Matthew Angyal, Norman Robson, James Pape, Joyeeta Nag, Alberto Cestero, Sandeep Torgal, Subramanian S. Iyer, K P Sarath Lal, John M. Safran, Giri N. K. Rangan, Thuy Tran-Quinn, Troy L. Graves-Abe, Gary W. Maier, Venkata Nr Vanukuru, Vikram Chaturvedi, Sami Rosenblatt, Shahid Butt
Publikováno v:
2016 IEEE 66th Electronic Components and Technology Conference (ECTC).
High performance processors and ASICs typically require multiple voltages and multi-domain voltage controls across the die. Conventional approaches distribute the voltage regulation elements between the processor, the package laminate, and the printe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::22ccba022f136a5c9ca925d3401cd501
https://doi.org/10.1109/ectc.2016.324
https://doi.org/10.1109/ectc.2016.324
Autor:
Troy L. Graves-Abe, Prakash Periasamy, Michael Iwatake, Joyce C. Liu, Menglu Li, Thuy Tran Quinn, Subramanian S. Iyer
Publikováno v:
2016 IEEE 66th Electronic Components and Technology Conference (ECTC).
Through Silicon Vias (TSV) is a key enabler for interposer and 3Di technologies. As the TSV process integration is maturing, reliability is a key parameter to be studied. One such reliability wear-out mechanisms is electro-migration (EM). In this pap
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0dfa820df888868460045aaf6edc7f52
https://doi.org/10.1109/ectc.2016.293
https://doi.org/10.1109/ectc.2016.293
Autor:
Koushik Ramachandran, Robert J. Gauthier, Thuy Tran-Quinn, You Li, Christy S. Tyberg, Matthew Angyal, Joel Abraham Silberman, Ephrem G. Gebreselasie, Katsuyuki Sakuma, Souvick Mitra
Publikováno v:
Scopus-Elsevier
A Design of Experiments (DOEs) matrix was created to evaluate probability of fails during a complex 3D integration process as a function of ESD protection level. A detailed set of pass/fail criteria based on circuit performance was established. Based
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::26c2916a0cb044455f603ec1f51f6ced
https://doi.org/10.1109/eosesd.2015.7314791
https://doi.org/10.1109/eosesd.2015.7314791
Akademický článek
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Autor:
M. Lakritz, Thuy Tran-Quinn
Publikováno v:
2008 IEEE/SEMI Advanced Semiconductor Manufacturing Conference.
Environmental concerns regarding saturated hydrocarbons has resulted in unsaturated hydrocarbons in the etching process such as C4F6. Higher costs and more exacting environmental resist conditions have made this difficult. It has been noted though, i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0d7b7416a9f596767de9d3b5e77e5235
https://doi.org/10.1109/asmc.2008.4529003
https://doi.org/10.1109/asmc.2008.4529003
Process integration issues for advanced contact etch of a .25 μm BiCMOS application in manufacturing
Publikováno v:
2004 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (IEEE Cat. No.04CH37530).
The contact etch module for BiCMOS device is one of the most critical modules. The process window involves several steps, including insulator thickness and uniformity, photolithography, etch and post etch treatments used to make contact to the front
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0d3b8a60931687513952405c95ad8763
https://doi.org/10.1109/asmc.2004.1309538
https://doi.org/10.1109/asmc.2004.1309538
Autor:
M.S. Fung, P. Kellawon, Thuy Tran-Quinn, D. Szmyd, David F. Hilscher, V. Saikuma, R. Ketcheson, S. Calvelli, R. Cook, N. Bell, J.W. Andrews
Publikováno v:
Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI.
A localized product yield degradation was observed on 0.25um BiCMOS product and was found to correlate to suppression of the NPN base and emitter currents. The addition of an ozone plasma clean prior to emitter polysilicon deposition helped to improv
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1b98ccee443d6116e846349b791783b5
https://doi.org/10.1109/asmc.2003.1194509
https://doi.org/10.1109/asmc.2003.1194509