Performance and Low-Frequency Noise of 22-nm FDSOI Down to 4.2 K for Cryogenic Applications

Autor: Tristan Meunier, Mikael Casse, Fred Gaillard, Silvano De Franceschi, Maud Vinet, Thorsten Kammler, Christoforos G. Theodorou, L. Pirro, Gerard Ghibaudo, Bruna Cardoso Paz

Publikováno v: IEEE Transactions on Electron Devices
IEEE Transactions on Electron Devices, Institute of Electrical and Electronics Engineers, 2020, 67 (11), pp.4563-4567. ⟨10.1109/TED.2020.3021999⟩
IEEE Transactions on Electron Devices, 2020, 67 (11), pp.4563-4567. ⟨10.1109/TED.2020.3021999⟩

International audience; This work presents the performance and low-frequency noise (LFN) of 22-nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology. The experimental measurements and the analysis are performed as a function of temperature f

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::708b694d06bf0840770eb2e9e8c5635d
https://doi.org/10.1109/ted.2020.3021999

Low Power FDSOI Technology and Devices for RF Applications

Autor: Christoph Schwan, Andreas Huschka, Edward J. Nowak, Laegu Kang, Rick Carter, David L. Harame, Mckay Thomas G, R. Taylor, Thomas Feudel, Kok Wai Johnny Chew, Jon Kluth, Josef S. Watts, Thorsten Kammler, Juergen Faul

Publikováno v: ECS Transactions. 75:21-27

We report RF Characteristics in a Low Power High Performance Ultra-thin Body and Box (UTBB) FDSOI technology. The technology features Si-Channel nFETs and SiGe-Channel pFETS, a gate first HiKMG stack with a gate length (LG) of 20nm, BOX thickness (TB

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1fc661d06a387fa0dd44e0df2a208435
https://doi.org/10.1149/07508.0021ecst

Versatile technology modeling for 22FDX platform development

Autor: Thorsten Kammler, Francis Benistant, M. H. J. Goh, Alban Zaka, L. Jiang, G. Kluth, J. Mazurier, I. Cortes, Jamie Schaeffer, Peter Javorka, Tom Herrmann, S. Deb Roy, Edmund R. Nowak, B. Rice, Jan Hoentschel, L. Pirro, David Harame, El Mehdi Bazizi

Publikováno v: 2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

The 22FDX platform offered by GLOBALFOUNDRIES consists of a family of differentiated products architected to enable applications across a variety of market segments such as RF & Analog, Ultra-low Power (ULP), and Ultra-low Leakage (ULL). In order to

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a20623fbc4c086aa1ae1f0e57a314894
https://doi.org/10.23919/sispad.2017.8085340

22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications

Autor: I. Aydin, C. Weintraub, J. Schmidt, Elke Erben, Hans-Jürgen Thees, Jamie Schaeffer, J. Kluth, T. Heller, C. Metze, R. Mulfinger, S. Nielsen, Jan Hoentschel, Thomas Feudel, Jürgen Faul, Rick Carter, J. Bernard, Peter Javorka, L. Pirro, David Harame, G. Grasshoff, S. Morvan, B. Rice, Carsten Grass, J-U. Sachse, Elliot John Smith, Mahbub Rashed, C. Bao, R. Nelluri, L. M-Meskamp, J. Mazurier, Yogadissen Andee, Thorsten Kammler, E. Bourjot, A. Preusse, Heimanu Niebojewski, Maud Vinet, P-Y. Chou, Peter Baars, R. Taylor

Publikováno v: 2016 IEEE International Electron Devices Meeting (IEDM)

22FDX™ is the industry's first FDSOI technology architected to meet the requirements of emerging mobile, Internet-of-Things (IoT), and RF applications. This platform achieves the power and performance efficiency of a 16/14nm FinFET technology in a

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::694b50f52b286e0ad5957b2cb925a715
https://zenodo.org/record/1272091

Control of topography and morphology for channel SiGe by in-situ HCl etching for future CMOS technologies with high-K metal gate

Autor: Gunda Beernink, Carsten Reichel, Thorsten Kammler, Stephan Kronholz, Annekathrin Zeun

Publikováno v: Solid-State Electronics. 60:134-138

In high- K metal gate-first integration for future CMOS technologies an epitaxial SiGe layer in the P -channel is applied to modulate V T . This results in an unwanted elevation of the P -channel challenging particularly gate patterning. In this work

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::5d412ac33e697c34c2458598cc012a9e
https://doi.org/10.1016/j.sse.2011.01.018