Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Thomas W. Andre"'
Autor:
J. J. Sun, M. DeHerrera, G. Shimon, Frederick B. Mancoff, J. Janesky, H. K. Lee, Syed M. Alam, Sanjeev Aggarwal, H. Lu, Brian M. Hughes, Kerry Joseph Nagel, Hamid Almasi, Thomas W. Andre, Sumio Ikegawa
Publikováno v:
2019 IEEE International Electron Devices Meeting (IEDM).
In this paper, we describe a fully-functional 1 Gb standalone spin-transfer torque magnetoresistive random access memory (STT-MRAM) integrated on 28 nm CMOS and based on perpendicular magnetic tunnel junctions (pMTJ’s). Electrical short flows were
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::585be30e388557e05d855de226372384
https://doi.org/10.1109/iedm19573.2019.8993516
https://doi.org/10.1109/iedm19573.2019.8993516
Autor:
Jon M. Slaughter, J. J. Sun, Sarin A. Deshpande, N. L. Chung, M. Hossain, Frederick B. Mancoff, Renu Whig, Sumio Ikegawa, Y. S. You, S. T. Woo, C. C. Wang, J. Wong, Naganivetha Thiyagarajah, T. Ling, J. W. Ting, H.-J. Chia, G. Shimon, J. Janesky, Ming-Wei Lin, Chim Seng Seet, H. Yang, Michael Tran, Syed M. Alam, Vinayak Bharat Naik, H. Lu, Thomas W. Andre, Taiebeh Tahmasebi, C. Hai, T. H. Chan, Dimitri Houssameddine, K. Yamane, Rajesh R. Nair, Danny Pak-Chum Shum, S. Y. Siah, K. W. Wong, M. DeHerrera, R. Chao, Sanjeev Aggarwal, Kerry Joseph Nagel, Kangho Lee
Publikováno v:
2017 Symposium on VLSI Technology.
Perpendicular Spin-Transfer Torque (STT) MRAM is a promising technology in terms of read/write speed, low power consumption and non-volatility, but there has not been a demonstration of high density manufacturability at small geometries. In this pape
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a8418750ba7a8213eb54d445cb6c292c
https://doi.org/10.23919/vlsit.2017.7998174
https://doi.org/10.23919/vlsit.2017.7998174
Autor:
Chitra K. Subramanian, Bradley J. Garni, Syed M. Alam, Joseph J. Nahas, W.L. Martino, K. Papworth, Thomas W. Andre, H. Lin
Publikováno v:
CICC
A 180 Kbit magnetoresistive random access memory (MRAM) organized as 22 bits by 8 Kwords has been developed for embedding in a 0.28 micron CMOS process. The memory cell is based on a 1-transistor 1-magnetic tunnel junction (1T1MTJ) bit cell with a to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d53da33526c34dc27017712222b99d82
https://doi.org/10.1109/jssc.2008.925408
https://doi.org/10.1109/jssc.2008.925408
Autor:
Joseph J. Nahas, W.L. Martino, Chitra K. Subramanian, Thomas W. Andre, H. Lin, A. Omair, Bradley J. Garni
Publikováno v:
IEEE Journal of Solid-State Circuits. 40:301-309
A 4-Mb toggle MRAM, built in 0.18-/spl mu/m five level metal CMOS technology, uses a 1.55 /spl mu/m/sup 2/ bit cell with a single toggling magneto tunnel junction to achieve a chip size of 4.5 mm /spl times/ 6.3 mm. The memory uses unidirectional pro
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c02c5ec0587e6d6d089b27e82f54cfeb
https://doi.org/10.1109/jssc.2004.837962
https://doi.org/10.1109/jssc.2004.837962
Autor:
X. Zhang, N. D. Rizzo, D. Gogl, Jon M. Slaughter, Thomas W. Andre, J. Janesky, Dimitri Houssameddine, Syed M. Alam, W. Meadows, Chitra K. Subramanian, H. Lin
Publikováno v:
CICC
Magnetoresistive Random Access Memory (MRAM) technology emerged from research and development into volume production within the last decade in the form of Toggle MRAM. The latest Magnetic Tunnel Junction (MTJ) based memory technology, Spin-Torque MRA
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a32cb1522c3fd4bdb06f0ca9e92e5836
https://doi.org/10.1109/cicc.2013.6658449
https://doi.org/10.1109/cicc.2013.6658449
Autor:
Frederick B. Mancoff, J. Janesky, Syed M. Alam, Thomas W. Andre, Kerry Joseph Nagel, J. J. Sun, Dimitri Houssameddine, P. LoPresti, Nicholas D. Rizzo, Sanjeev Aggarwal, Renu Whig, Jon M. Slaughter, Sarin A. Deshpande
Publikováno v:
2012 International Electron Devices Meeting.
We review key properties for commercial ST-MRAM circuits, discuss the challenges to achieving the many performance and scaling goals that are being addressed in current development around the world, recent results in the field, and present first resu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::81b57c650545db6924d7accfddca6370
https://doi.org/10.1109/iedm.2012.6479128
https://doi.org/10.1109/iedm.2012.6479128
Autor:
K. Smith, C. Frey, B. Feil, T. Ditewig, J. J. Sun, J. Chan, R. Fournel, R. Cuppens, Mark A. Durlam, D. Galpin, L. Wise, Saied N. Tehrani, M. Lien, Mark F. Deherrera, J. Tamim, Thomas W. Andre, J. Calder, Gloria Kerszykowski, Joseph J. Nahas, K. Nagel, R. Williams, B. Martino, Bradley J. Garni, S. Zoll, Jason Allen Janesky, Chitra K. Subramanian, J. Martin, Renu W. Dave, F. List, B.N. Engel, P. Brown, G. Grynkewich
Publikováno v:
Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..
A 90nm magnetoresistive random access memory (MRAM) based on the toggle switching mode has been successfully demonstrated for the first time in a 90nm CMOS process. The MRAM memory cell is based on a 1-transistor 1-magnetic tunnel junction (1T1MTJ) w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b774146b05cdf49fe162d07dbfe6101b
https://doi.org/10.1109/.2005.1469261
https://doi.org/10.1109/.2005.1469261
Autor:
W. Martino, Halbert S. Lin, Thomas W. Andre, Chitra K. Subramanian, Joseph J. Nahas, Bradley J. Garni, A. Omair
Publikováno v:
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
The 4.5/spl times/6.3mm/sup 2/ 25ns cycle-time 4Mb Toggle MRAM memory, built in 0.18 /spl mu/m 5M CMOS technology, uses a 1.55 /spl mu/m/sup 2/ bit cell with a single toggling magneto tunnel junction. The memory uses uni-directional programming curre
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::62ace88d4b07057137c7efccf4c68667
https://doi.org/10.1109/isscc.2004.1332585
https://doi.org/10.1109/isscc.2004.1332585
Autor:
A. Omair, Joseph J. Nahas, W.L. Martino, Thomas W. Andre, Bradley J. Garni, Chitra K. Subramanian, H. Lin
Publikováno v:
2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866).
A 4 Mbit "Toggle" MRAM, built in 0.18 micron five level metal CMOS technology, using a 1.55 /spl mu/m/sup 2/ bitcell with a single toggling magneto tunnel junction is described. The "Toggle" memory uses unidirectional programming currents controlled
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::db4138e07d0ac79d291bbfd36786fea1
https://doi.org/10.1109/icicdt.2004.1309940
https://doi.org/10.1109/icicdt.2004.1309940