Zobrazeno 1 - 10
of 15
pro vyhledávání: '"Thomas J. Haigh"'
Autor:
K. Sharma, Thomas J. Haigh, Dennis M. Hausmann, James J. Demarest, Peethala Cornelius Brown, Paul C. Lemaire, James Chingwei Li, Arpan Mahorowala, Hosadurga Shobha, Hsiang-Jen Huang, Balasubramanian S. Pranatharthi Haran, Son V. Nguyen, P. Ramani
Publikováno v:
2021 IEEE International Interconnect Technology Conference (IITC).
AlOx was selectively deposited on top of SiCOH in 32 nm pitch Cu-SiCOH pattern to form a Fully Aligned Via (FAV) test structure. Selective deposition process performance and its integration into the 5nm BEOL FAV structure were evaluated. The selectiv
Autor:
Hosadurga Shobha, Donald F. Canaperi, Chao-Kun Hu, Son V. Nguyen, Junedong Lee, Eric G. Liniger, Yongjin Yao, Griselda Bonilla, Chen Jia, Takeshi Nogami, Huai Huang, Stephan A. Cohen, B. Peethala, Theodorus E. Standaert, Thomas J. Haigh
Publikováno v:
2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).
Mechanically robust low k C-rich SiCN and pSiCN dielectrics with excellent built-in Cu oxidation and diffusion barrier have been developed and evaluated as potential alternative low k Interlevel dielectrics for Cu interconnects. The novel low k dense
Autor:
Thomas J. Haigh, Kangguo Cheng, Liying Jiang, James Chingwei Li, Chanro Park, Christopher J. Penny, Don Canaperi, Son V. Nguyen, Sanjay Mehta, Tenko Yamashita
Publikováno v:
ECS Transactions. 85:25-39
Publikováno v:
ECS Transactions. 75:5-13
Autor:
Paul S. McLaughlin, Thomas J. Haigh, Devika Sil, Huai Huang, Nicholas A. Lanzillo, Raghuveer R. Patlolla, Pranita Kerber, Hosadurga Shobha, James Chingwei Li, C. B. Pcethala, Yongan Xu, Donald F. Canaperi, James J. Demarest, Elbert E. Huang, Chanro Park, Clevenger Leigh Anne H, Benjamin D. Briggs, Licausi Nicholas, Jae Gon Lee, M. Ali, Son Nguyen, Young-Wug Kim, Theodorus E. Standaert, C. T. Le, G. Lian, Griselda Bonilla, Errol Todd Ryan, Han You, David L. Rath
Publikováno v:
2018 IEEE International Interconnect Technology Conference (IITC).
As BEOL pitch continues to aggressively scale, contributions from pattern dimension and edge placement constrict the available geometry of interconnects. In particular, the critical minimum insulator spacing which defines a technologies max operating
Autor:
David L. O'Meara, Thomas J. Haigh, Paul Hall, Kyle Dwyer, Paul Higgins, Jean E. Wynne, Josh Prendergast, John Grassucci, Jessica Gruss-Gifford
Publikováno v:
2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
Particle defects in the form of foreign material (FM) are a common occurrence in semiconductor manufacturing. This work discusses the strategies used to detect the source of FM particles in a room temperature oxide furnace. FM particles were measured
Autor:
Yongan Xu, Peethala Cornelius Brown, Hosadurga Shobha, Chanro Park, Huai Huang, Devika Sil, Pranita Kerber, Raghuveer R. Patlolla, David L. Rath, Clevenger Leigh Anne H, M. Ali, James Chingwei Li, Jae Gon Lee, Paul S. McLaughlin, Benjamin D. Briggs, Thomas J. Haigh, C. T. Le, G. Lian, Theodorus E. Standaert, Son Nguyen, Nicholas A. Lanzillo, Licausi Nicholas, Donald F. Canaperi, Elbert E. Huang, Errol Todd Ryan, Han You, Griselda Bonilla, James J. Demarest, Young-Wug Kim
Publikováno v:
2017 IEEE International Electron Devices Meeting (IEDM).
A fully aligned via (FAV) integration scheme is introduced and demonstrated at 36 nm metal pitch, with extendibility to beyond the 7 nm node. Selective chemistries were developed to recess Cu and W wires and their associated barrier liner materials,
Autor:
Griselda Bonilla, Chenming Hu, Thomas J. Haigh, C. Zahakos, Steven E. Molis, Thomas M. Shaw, Steve Cohen, Eric G. Liniger, Chet Dziobkowski, N. Klymko, Hosadurga Shobha, Alfred Grill, Son V. Nguyen
Publikováno v:
ECS Transactions. 33:137-145
The scaling limit of plasma enhanced chemical vapor deposited (PECVD) ultrathin(5-35 nm) silicon carbon nitride (SiCNH) dielectric as an oxidation and Cu diffusion barrier for damascene process is explored. The SiCNH cap's electrical properties, oxid
Autor:
Son van Nguyen, Thomas J Haigh, Kangguo Cheng, C. Penny, Chanro Park, Sanjay C Mehta, Tenko Yamashita, Liying Jiang, Don Canaperi
Publikováno v:
ECS Meeting Abstracts. :1371-1371
EXTENDED ABSTRACT Continued integrated circuit scaling deeper into the nanoscale regime has provided improved performance through shrinking of the Front-End-of-Line (FEOL) device and Back-End-of-Line (BEOL) interconnect. With scaling, resistance-capa
Autor:
Timothy M. Shaw, Thomas J. Haigh, Stephan A. Cohen, Leo Tai, Shobha Hosadugra, Donald F. Canaperi, Yongjin Yao, Son V. Nguyen, Kumar Virwani, Andrew J. Kellock, Chao-Kun Hu, Eric G. Liniger
Publikováno v:
ECS Meeting Abstracts. :1260-1260
The metallization of integrated circuits for high performance CMOS devices involves the use of copper with low-k or ultra low-k dielectrics to reduce RC delay and cross talk in devices. For the 90nm to 14 nm CMOS device nodes, conventional silicon ni