Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Theodore Letavic"'
Publikováno v:
Philips Journal of Research. 49:91-124
Film quality and crystalline perfection of SOI layers obtained by bonding and etch back silicon-on-insulator (BESOI) technology have been studied. In particular, the various mechanisms of defect generation that contribute to a degradation of the orig
Publikováno v:
Philips Journal of Research. 49:125-138
The incorporation of strain is inherent in the manufacture of bond and etchback silicon-on-insulator (BESOI) substrates. In this paper, the principal sources of strain are identified and the magnitude of the strain is estimated. The strain sources di
Publikováno v:
IEEE Electron Device Letters. 20:490-492
Temperature dependence of saturation velocity in bulk silicon and in surface-accumulation layers was studied between room temperature and 600 K. The saturation electron velocity in bulk silicon was found to have a steeper temperature dependence than
Publikováno v:
2006 IEEE International Symposium on Power Semiconductor Devices & IC's.
This paper presents a thin-layer high voltage silicon-on-insulator conductivity modulated device which has been optimized for use within integrated switch mode power supply applications. The device contains a linearly-graded charge profile in the dri
Autor:
Helmut Baumgart, S. Merchant, R. Egloff, Emil Arnold, Theodore Letavic, Satyendranath Mukherjee, H. Pein
Publikováno v:
IEEE International SOI Conference.
Publikováno v:
IEEE Electron Device Letters. 17:557-559
High-temperature off-state characteristics of thin-SOI RESURF LDMOS transistors were studied experimentally and theoretically and compared with off-state characteristics of junction-isolated bulk-Si power devices. At 200/spl deg/C, the off-state leak
Publikováno v:
ISPSD '03. 2003 IEEE 15th International Symposium on Power Semiconductor Devices and ICs, 2003. Proceedings..
This report describes the novel use of the field-plate in a SOI HV power FET as a V/sub DS/ sensing terminal. The sensing terminal can be used in over-voltage protection schemes without the need of an external clamping circuit. We have shown that thi
Autor:
R. Albu, I. Weijland, Theodore Letavic, Benoit Dufort, H. van Zwol, Satyendranath Mukherjee, Mark Simpson, John Petruzzello
Publikováno v:
Proceedings of the 14th International Symposium on Power Semiconductor Devices and Ics.
We present a thin-layer silicon-on-insulator (SOI) high-voltage PMOS device structure and measured performance characteristics. The all-implanted device structure supports voltage by multi-dimensional depletion from a combination of implanted surface
Autor:
Erik Peters, Mark Simpson, S. Herko, R. Aquino, Emil Arnold, Satyendranath Mukherjee, Theodore Letavic, J. Curcio
Publikováno v:
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312).
An integrated 600 V power conversion system is described based on smart power technology which combines novel lateral high-voltage RESURF transistor structures and a merged bipolar/CMOS/DMOS process flow on thin-layer SOI substrates. A new high-volta
Autor:
H. Bhimnathwala, Satyendranath Mukherjee, R. Egloff, Helmut Baumgart, Theodore Letavic, S. Merchant, Emil Arnold
Publikováno v:
Proceedings of 1993 IEEE International SOI Conference.
The recombination properties of minority carriers determine the basic electronic properties of SOI materials and control the performance of a variety of SOI devices. Knowledge of the minority carrier recombination characteristics and its correlation