Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Theo J. Powell"'
Publikováno v:
ITC
A design's increasing density, as well as its number of embedded memories increases its vulnerability to a variety of potential manufacturing defects. Standard March test algorithms used for obtaining good defect coverage must be augmented by new alg
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https://explore.openaire.eu/search/publication?articleId=doi_________::8ba26bb52b0440d8d52368f6ec2b75f2
https://doi.org/10.1109/test.2005.1584048
https://doi.org/10.1109/test.2005.1584048
Publikováno v:
ITC
Today’s ASIC designs consist of more memory in terms of both area and number of instances. The shrinking of geometries has an even greater effect upon memories due to their tight layouts. These two trends are putting much greater demands upon memor
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a6d0d397dc03eacbf39833e2613b6f96
https://doi.org/10.1109/test.2003.1270862
https://doi.org/10.1109/test.2003.1270862
Publikováno v:
ITC
The TMS370 family of microcomputers was designed with a requirement for >99% stuck fault coverage. A design for testability (DFT) methodology called parallel/serial scan design was used which partitioned the design into independently testable modules
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https://explore.openaire.eu/search/publication?articleId=doi_________::173d4eb4e1288051991080097337607f
https://doi.org/10.1109/test.1988.207793
https://doi.org/10.1109/test.1988.207793
Publikováno v:
ITC
Functional tests and I/sub DDQ/ tests are studied to determine their effectiveness toward screening failures. A model is presented for curve fitting correlation data between fault coverages and defect quality employing the Williams and Brown defect l
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https://doi.org/10.1109/test.1996.557075
https://doi.org/10.1109/test.1996.557075
Autor:
Theo J. Powell
Publikováno v:
VTS
Unknown values result from floating and contention type faults on tristate buffer nets thereby causing MISR signature loss during test pattern compression. A Consistently Dominant Fault model is presented that removes the problem and permits fault de
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4b82ae4f180b5f6bcd4ac62927cdb73a
https://doi.org/10.1109/vtest.1996.510885
https://doi.org/10.1109/vtest.1996.510885
Publikováno v:
VTS
The Texas Instruments TMS370 is in volume production. Sample manufacturing data has been collected to correlate stuck fault grades to the defect levels that would have been realized at those grades, at both the module and chip levels. Since the chip
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c7e174dfad7e4d5fa894a05c3bb30999
https://doi.org/10.1109/vtest.1994.292314
https://doi.org/10.1109/vtest.1994.292314
Publikováno v:
ITC
The Disturb Test Algorithms are targeted for row adjacent coupled defects that can be time elapsed dependent. A BIST design is described for application of these tests for testing 256 Meg SDRAM chips.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::91167f93bb325d278b57255e89756653
https://doi.org/10.1109/test.1997.639614
https://doi.org/10.1109/test.1997.639614
Publikováno v:
ITC
The TMS320C80 is a programmable, parallel processing DSP. The test approach was an engineering mix of design for testability, test view creation, and verification. This mixture facilitated timely test generation and had other important benefits. We d
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https://doi.org/10.1109/test.1995.529828
https://doi.org/10.1109/test.1995.529828
Publikováno v:
VTS
Point defects, which cause small current increases and potentially early failures, can be masked by increased chip background currents at elevated temperatures. The difficulty of screening point defects will likely also occur in denser geometries. De
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b7453adf7751c032d3d625a6929ffa15
https://doi.org/10.1109/vtest.2000.843876
https://doi.org/10.1109/vtest.2000.843876
Publikováno v:
Computers & Mathematics with Applications. (5-6):537-545
Parallel signature analyzers (PSAs) implemented as multiple input linear feedback shift registers are very useful in compressing test response data in digital circuits. In this paper, some analytical results on error detection using a class of PSAs a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e188a8a15b5aa120433abde83e2c0246