Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Thawra Kadeed"'
Autor:
Biswadip Maity, Minjun Seo, Eberle A. Rambo, Nikil Dutt, Rolf Ernst, Florian Maurer, Andreas Herkersdorf, Anmol Prakash Surhonne, Thawra Kadeed, Bryan Donyanavard, Fadi J. Kurdahi, Caio Batista de Melo
Publikováno v:
IEEE Transactions on Emerging Topics in Computing. 10:250-266
In order to provide performance increases despite the end of Moore's law and Dennard scaling, architectures aggressively exploit data- and thread-level parallelism using billions of transistors on a single chip, enabled by extreme geometry miniaturiz
Publikováno v:
Integration. 65:1-17
The power overhead of Networks-on-Chip (NoCs) becomes tremendous in high density Multiprocessor Systems-on-Chip (MPSoCs). Especially in hard real-time and safety-critical systems, power management mechanisms must be developed and efficiently adhered
Publikováno v:
PRDC
In mixed-criticality real-time systems, system resources must be sufficiently separated to guarantee non-interference of critical functions. This leads to fixed boundaries between critical and non-critical parts of a system impeding change, repair, o
Publikováno v:
RTSS
While Networks-on-Chip (NoCs) are the prevalent solution to provide a scalable interconnect for the complex multiprocessing architectures, their associated energy consumptions have immensely increased. Specifically, hard real-time Networks-on-chip mu
Publikováno v:
RTCSA
Networks-On-Chip (NoCs) designed to host advanced embedded applications require simultaneously high performance and efficient real-time guarantees under tight power limitations. Static power management is no longer sufficient to fulfill these goals i
Autor:
Rolf Ernst, Thomas Wild, Thawra Kadeed, Amir M. Rahmani, Bryan Donyanavard, Armin Sadighi, Nikil Dutt, Ahmed Nassar, Fadi J. Kurdahi, Tiago Muck, Andreas Herkersdorf, Kasra Moazzemi
Publikováno v:
DATE
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)
This paper deals with challenges and possible solutions for incorporating self-awareness principles in EDA design flows for autonomous systems. We present a holistic approach that enables self-awareness across the software/hardware stack, from system
Publikováno v:
SoCC
As fault-tolerant Networks-on-Chip (NoCs) become prevalent in reliable systems, their overhead must be accurately evaluated. In this paper, we evaluate the overhead of a soft error resilient real-time NoC router for ASICs in terms of area and power.