Zobrazeno 1 - 10
of 32
pro vyhledávání: '"Thannirmalai Somu"'
Autor:
Weng-Fai Wong, Tao Luo, Matthew Lee, Wai Teng Tang, Rick Siow Mong Goh, Yingnan Cui, Jun Zhou, Thannirmalai Somu
Publikováno v:
ACM Transactions on Architecture and Code Optimization. 15:1-24
Advances in non-volatile resistive switching random access memory (RRAM) have made it a promising memory technology with potential applications in low-power and embedded in-memory computing devices owing to a number of advantages such as low-energy c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::41f2b9e828fcb7b77f57b791d33f170c
https://doi.org/10.1145/3291054
https://doi.org/10.1145/3291054
Autor:
Anuj Pathania, Thannirmalai Somu Muthukaruppan, Vanchinathan Venkataramani, Mihai Pricopi, Sanjay Vishin, Tulika Mitra
Publikováno v:
The Dark Side of Silicon ISBN: 9783319315942
The dark silicon era is driving the emergence of asymmetric computing platforms consisting of cores with diverse power-performance characteristics enabling better match between a task’s requirements and the compute engine leading to substantially i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f65a80791879b791803d4578b7b5619f
https://doi.org/10.1007/978-3-319-31596-6_6
https://doi.org/10.1007/978-3-319-31596-6_6
Autor:
Mitra, Tulika, Muthukaruppan, Thannirmalai Somu, Pathania, Anuj, Pricopi, Mihai, Venkataramani, Vanchinathan, Vishin, Sanjay
Publikováno v:
Dark Side of Silicon; 2017, p159-189, 31p
Publikováno v:
DFT
In this paper we present an architectural and on-line resource management solution to optimize lifetime reliability of asymmetric multicores while minimizing the system energy consumption, targeting both single nodes (multicores) as well as multiple
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6408ffe3bc47b10f8fad410ef61e1c6f
https://doi.org/10.1109/dft.2016.7684066
https://doi.org/10.1109/dft.2016.7684066
Publikováno v:
2016 IEEE International Symposium on Defect & Fault Tolerance in VLSI & Nanotechnology Systems (DFT); 2016, p35-40, 6p
Publikováno v:
ASP-DAC
The high performance demand of embedded systems along with restrictive thermal design power (TDP) constraint have lead to the emergence of the heterogenous multi-core architectures, where cores with the same instruction-set architecture but different
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1ef8254c6c270ca73e043311ecd2c79b
https://doi.org/10.1109/aspdac.2015.7059077
https://doi.org/10.1109/aspdac.2015.7059077
Publikováno v:
20th Asia & South Pacific Design Automation Conference; 2015, p618-623, 6p
Publikováno v:
ASPLOS
Heterogeneous multi-cores that integrate cores with different power performance characteristics are promising alternatives to homogeneous systems in energy- and thermally constrained environments. However, the heterogeneity imposes significant challe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3e9758953f192705bc335fdb1fc0e698
https://doi.org/10.1145/2541940.2541974
https://doi.org/10.1145/2541940.2541974
Publikováno v:
ICCD
In this paper, we propose a framework for synthesis of application specific MultiProcessor System on Chip (MPSoC) for multimedia applications. Our framework searches for a design with minimum energy consumption under area and period constraints. We s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::99df902d74115ce2f0b4236befc5139c
https://doi.org/10.1109/iccd.2013.6657026
https://doi.org/10.1109/iccd.2013.6657026
Autor:
Mihai Pricopi, Thannirmalai Somu Muthukaruppan, Vanchinathan Venkataramani, Tulika Mitra, Sanjay Vishin
Publikováno v:
2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9cbdcbc2e9af420a5a85c1f96cb76f53
https://doi.org/10.1109/cases.2013.6662519
https://doi.org/10.1109/cases.2013.6662519