Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Teva Stone"'
Autor:
Brian Tsang, Teva Stone, Masum Hossain, Farrukh Aquil, John Eble, Barry Daly, J. Wei, Chanh Tran, Kurt Knorpp, Pak Shing Chau, Jared L. Zerbe, Phuong Le
Publikováno v:
IEEE Journal of Solid-State Circuits. 49:1048-1062
A 800 Mb/s to 3.2 Gb/s memory interface is designed that achieves 30% improved energy efficiency by eliminating idle mode power completely. The link is similar to a standard DDR architecture with the addition of a fast-lock DLL on the memory side tha
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::51032f4b8a293ef08687cce598582226
https://doi.org/10.1109/jssc.2013.2297403
https://doi.org/10.1109/jssc.2013.2297403
Autor:
Teva Stone, Wayne Dettloff, B. William F. Stonecypher, Pravin Kumar Venkatesan, Chris Madden, Sanath Bangalore, Kambiz Kaviani, Yi Lu, Bruce Su, Kashinath Prabhu, Barry Daly, Nhat Nguyen, John Eble, Michael Bucher, Liji Gopalakrishnan, Ravi Kollipara, Fred Heaton, Lei Luo
Publikováno v:
ISSCC
The emergence of cloud computing has driven the demand for high-density, low-latency and high-speed memory interfaces. For such applications the use of multiple dual-inline memory modules (DIMMs) with multiple ranks enables time-efficient processing
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5ed036791ed31dc45a8cf56e04a0ce27
https://doi.org/10.1109/jssc.2013.2280308
https://doi.org/10.1109/jssc.2013.2280308
Autor:
Makarand Shirasgaonkar, Wayne Dettloff, Teva Stone, Jared L. Zerbe, Brian Tsang, Kambiz Kaviani, Kashinath Prabhu, Masum Hossain, Barry Daly, John Eble
Publikováno v:
CICC
A dynamic rate adjustable interface is designed a 40-nm LP CMOS process. On-the-fly dynamic rate change is enabled by an all-digital frequency multiplier that detects a reference frequency change, and accordingly provides 4× multiplied clock without
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::46a91d6a255d88b1dfda4287e8de35bd
https://doi.org/10.1109/cicc.2012.6330579
https://doi.org/10.1109/cicc.2012.6330579
Autor:
Teva Stone, Jared L. Zerbe, Lei Luo, Barry Daly, Patrick Satarzadeh, Michael Bucher, John Eble, Bill Stonecypher, Qi Lin, Brian S. Leibowitz, Wayne Dettloff, Jihong Ren
Publikováno v:
2010 Symposium on VLSI Circuits.
A 5Gb/s signaling system was designed and fabricated in TSMC's 40nm LP CMOS process. A new clock/data skew minimization technique with a source-synchronous transmit clock delay line and integrating receiver tolerates high frequency transmit clock jit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3fad6b0f51d52c5284d2f929c6f2c20e
https://doi.org/10.1109/vlsic.2010.5560280
https://doi.org/10.1109/vlsic.2010.5560280
Publikováno v:
ISSCC
Source-series-terminated (SST) transmitters consume ¼ the output stage power of CML drivers [1], but their adoption in industry-standard multi-protocol SerDes has been stunted by difficulties in achieving flexible swings, constant current equalizati
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::96c39e371d7ec5f4ae0590391e5788b7
https://doi.org/10.1109/isscc.2010.5433825
https://doi.org/10.1109/isscc.2010.5433825
Autor:
R. Rathi, Teva Stone, Ramin Farjad-Rad, John W. Poulton, D. Huang, H. Mg, E. Lee, William J. Dally, R. Nathan
Publikováno v:
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
The MDLL, in 0.18 /spl mu/m CMOS, has 0.05 mm/sup 2/ active area and 200 MHz to 2 GHz speed range. The complete synthesizer, including the output clock buffers, dissipates 12 mW from a 1.8 V supply at 2.0 GHz. This MDLL architecture is used as a cloc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fb4df5ea775d9fbcbc1e6d7cd2f0b27d
https://doi.org/10.1109/isscc.2002.992946
https://doi.org/10.1109/isscc.2002.992946