Zobrazeno 1 - 10
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pro vyhledávání: '"Test compression"'
Akademický článek
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Autor:
Kuen-Jong Lee, Sudhakar M. Reddy, Chong-Siao Ye, Shi-Xuan Zheng, Janusz Rajski, Wu-Tung Cheng, Justyna Zawada, Mark Kassab, Chen Wang, Fong-Jyun Tsai
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 41:2323-2336
Test costs for large industrial designs increase rapidly in recent years. On-chip test compression hardware has become a pragmatic technology to cut down the overall test costs by reducing test data volume. Determining the input and output channel co
Publikováno v:
Media Komunikasi Teknik Sipil, Vol 22, Iss 1, Pp 35-42 (2016)
The change of temperature is quite high, as was the case in the event of a fire, it will have an impact on the concrete structure. Because in the process there will be a cycle of alternately heating and cooling, which would lead to a change in phase
Externí odkaz:
https://doaj.org/article/49d1bffe6a4848029e1adffe79085bd1
Autor:
Janusz Rajski, Yingdi Liu, Grzegorz Mrugalski, Sylwester Milewski, Bartosz Wlodarczak, Nilanjan Mukherjee, Jerzy Tyszer
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 29:1553-1566
Hybrid test schemes comprising on-chip test compression and logic built-in self-test are expected to play a pivotal role in the design of new integrated circuits and delivering high quality tests. As architectural differences between these two paradi
Autor:
Maciej Trawka, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Sylwester Milewski, Janusz Rajski
Publikováno v:
IEEE Transactions on Emerging Topics in Computing. 9:680-691
The semiconductor industry ramping up design capabilities for emerging technologies is facing new test quality and yield management challenges. To facilitate debugging of the first silicon, diagnosis of yield issues, and to enable repair processes, a
Conference
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Publikováno v:
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Universitat Politècnica de Catalunya (UPC)
In-system deterministic tests are used in safetysensitive designs to assure high test coverage, short test time, and low data volume, typically through an input-streaming-only approach that allows a quick test delivery. The output side of the same sc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::058f6b048df11862d14d9e6f11a4543c
https://hdl.handle.net/2117/372136
https://hdl.handle.net/2117/372136
Publikováno v:
IEEE Transactions on Instrumentation and Measurement. 70:1-12
This article presents an advanced method for monolithic 3-D integrated circuits (ICs)’ test compression based on 3-D Haar wavelet transforms. The main purpose of this study is to reduce the test response data consumption while achieving higher faul
Publikováno v:
Journal of Electronic Testing. 36:577-590
High temperature during test mode and the large volume of test data are the two prominent challenges in the testing of System-on-Chip (SoC). Temperature relies on the spatial power distribution between the blocks of the chip. An efficient don’t car
Autor:
AKDOĞAN, Erkin, ŞAHBAZ, Mehmet
Publikováno v:
Issue: 34 739-744
Avrupa Bilim ve Teknoloji Dergisi
Avrupa Bilim ve Teknoloji Dergisi
Bu çalışmada bir Aşırı Plastik Deformasyon (Severe Plastic Deformation-SPD) yöntemi olan Çok Yönlü Dövme (Multi-Directional Forging ‘MDF’) işleminin AA5083 alüminyum alaşımına uygulanması deneysel olarak incelenmiştir. MDF işle