Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Teruhiko Amano"'
Autor:
Teruhiko Amano, Hiroyuki Kawai, Masaya Shirata, Koji Nii, Yuji Yano, Yasuto Kuroda, Hideyuki Noda, Isamu Hayashi, Katsumi Dosaka, Naoya Watanabe
Publikováno v:
IEEE Journal of Solid-State Circuits. 48:2671-2680
An 18-Mb full ternary CAM with low-voltage matchline sensing scheme (LVMLSS) is designed and fabricated in 65-nm bulk CMOS process. LVMLSS has three key techniques: voltage down converter, differential sense amplifier with matchline isolation, and re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7912c68b7bd3705736d057b2328c7193
https://doi.org/10.1109/jssc.2013.2274888
https://doi.org/10.1109/jssc.2013.2274888
Autor:
Akira Yamazaki, Atsushi Hachisuka, Katsumi Dosaka, Tsutomu Yoshihara, Teruhiko Amano, Hideyuki Ozaki, Naoya Watanabe, Hideyuki Noda, Masaru Haraguchi, Kazutami Arimoto, Fukashi Morishita, Setsuos Wake
Publikováno v:
IEICE Transactions on Electronics. :2020-2027
The voltage margin of an embedded DRAM's sense operation has been shrinking with the scaling of process technology. A method to estimate this margin would be a key to optimizing the memory array configuration and the size of the sense transistor. In
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2164b4ddefa9f4233c32a65d7e165ef9
https://doi.org/10.1093/ietele/e88-c.10.2020
https://doi.org/10.1093/ietele/e88-c.10.2020
Autor:
Yasuto Kuroda, Hideyuki Noda, Teruhiko Amano, Koji Nii, Hiroyuki Kawai, Katsumi Dosaka, Masaya Shirata, Isamu Hayashi, Koji Hayano, Naoya Watanabe, Sizuo Morizane, Yuji Yano
Publikováno v:
2012 IEEE Asian Solid State Circuits Conference (A-SSCC).
An 18Mb full ternary CAM with low voltage match line sense amplifier (LV-MA) is designed and fabricated in 65-nm bulk CMOS process. The die size is 99.06 mm2. The proposed LV-MA reduces the dynamic power consumption of match-lines to 33% compared to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d4c62d55d2c2d4af92b4920ed43b70e2
https://doi.org/10.1109/ipec.2012.6522628
https://doi.org/10.1109/ipec.2012.6522628
Publikováno v:
Scopus-Elsevier
A new method for exciting surface plasmon polaritons (SPP's) on a metal surface without using a prism coupler is experimentally tested. The method uses a layer of metallic nanoparticles placed on the metal surface. A thin layer of SiO2 containing Ag
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::44c8d0f6abd6f79366ae7eee10948803
http://www.scopus.com/inward/record.url?eid=2-s2.0-0030105750&partnerID=MN8TOARS
http://www.scopus.com/inward/record.url?eid=2-s2.0-0030105750&partnerID=MN8TOARS
Autor:
Hayashi, Shinji, Kume, Tetsuji, Teruhiko Amano, Teruhiko Amano, Keiichi Yamamoto, Keiichi Yamamoto
Publikováno v:
Japanese Journal of Applied Physics; March 1996, Vol. 35 Issue: 3 pL331-L331, 1p
Conference
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Publikováno v:
2014 2nd International Conference on Devices, Circuits & Systems (ICDCS); 2014, p1-6, 6p
Autor:
Kuge, S., Kato, T., Furutani, K., Kikuda, S., Mitsui, K., Hamamoto, T., Setogawa, J., Hamade, K., Komiya, Y., Kawasaki, S., Kono, T., Amano, T., Kubo, T., Haraguchi, M., Kawaguchi, Z., Nakaoka, Y., Akiyama, M., Konishi, Y., Ozaki, H.
Publikováno v:
2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056); 2000, p402-474, 4p
Autor:
Hayashi, Isamu, Amano, Teruhiko, Watanabe, Naoya, Yano, Yuji, Kuroda, Yasuto, Shirata, Masaya, Dosaka, Katsumi, Nii, Koji, Noda, Hideyuki, Kawai, Hiroyuki
Publikováno v:
IEEE Journal of Solid-State Circuits; Nov2013, Vol. 48 Issue 11, p2671-2680, 10p
Autor:
Yamauchi, T., Kinoshita, M., Amano, T., Dosaka, K., Arimoto, K., Ozaki, H., Yamada, M., Yoshihara, T.
Publikováno v:
IEEE Journal of Solid-State Circuits; Jan2001, Vol. 36 Issue 1, p46-54, 9p