Zobrazeno 1 - 3
of 3
pro vyhledávání: '"Terence G. W. Blake"'
Autor:
Yunchen Qiu, R. Acklin, Xiao-Hong Du, K. Remack, Anand Seshadri, John Y. Fong, D. Liu, W.F. Kraus, J. Roscher, Terence G. W. Blake, Scott R. Summerfelt, S. Natarajan, Sudhir K. Madan, J. Eliason, Ning Qian, J. Rodriguez, Theodore S. Moise, Hugh P. McAdams
Publikováno v:
IEEE Journal of Solid-State Circuits. 39:667-677
A low-voltage (1.3 V) 64-Mb ferroelectric random access memory (FRAM) using a one-transistor one-capacitor (1T1C) cell has been fabricated using a state-of-the-art 130-nm transistor and a five-level Cu/flouro-silicate glass (FSG) interconnect process
Publikováno v:
IEEE Journal of Solid-State Circuits. 31:430-436
A scaleable gate array has been designed in half-micron CMOS for a wide range of high-speed and high-density applications. Transistor size and position within the basecell provide an efficient implementation of flip-flops, combinational gates, and me
Autor:
Theodore S. Moise, Xiao-Hong Du, Scott R. Summerfelt, Ralph H. Lanham, Jürgen T. Rickes, R. Acklin, J. Eliason, C. Pietrzyk, Hugh P. McAdams, John Y. Fong, Y. Qui, N. Qian, Anand Seshadri, S. Natarajan, Sudhir K. Madan, J. Roscher, F. Li, W.F. Kraus, D. Liu, Terence G. W. Blake
Publikováno v:
2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).
A low-voltage (1.3V), 64 Mbit Ferroelectric Random Access Memory using a 1-transistor, 1-capacitor (1T1C) cell is demonstrated. This is the largest FRAM memory demonstrated to date. The memory is constructed using a state-of-the-art 130 nm transistor