Zobrazeno 1 - 10
of 103
pro vyhledávání: '"Terence B. Hook"'
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 4, Iss 5, Pp 266-272 (2016)
Vertically stacked nanowire field effect transistors currently dominate the race to become mainstream devices for 7-nm CMOS technology node. However, these devices are likely to suffer from the issue of nanowire stack position dependent drain current
Externí odkaz:
https://doaj.org/article/d8e947e71a8f48ddb603296ce72da2ee
Publikováno v:
IEEE Transactions on Electron Devices. 67:2208-2212
Application of high-frequency ac stress in the place of conventional dc stress is known to decrease the damage caused by self-heating (SH)-induced hot-carrier injection (HCI) in highly scaled MOSFET devices. However, the effect of hot-carrier degrada
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f02eb5fefc098bbc53bf8a52edfd0f60
https://doi.org/10.1109/ted.2020.2977734
https://doi.org/10.1109/ted.2020.2977734
Autor:
Ji Kai Wang, Prasad S. Gudem, Michael Wong, Zhi Cheng Yuan, Terence B. Hook, Paul M. Solomon, Mani Vaidyanathan, Diego Kienle
Publikováno v:
IEEE Transactions on Electron Devices. 66:2028-2035
Ferroelectric and negative-capacitance field-effect transistors (FeFETs and NCFETs) have recently garnered great attention as devices for applications in memory and low-power logic, respectively. As these technologies are pursued, it is critical to h
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7a7b3548250cebcf7931a3edfa83cde9
https://doi.org/10.1109/ted.2019.2901668
https://doi.org/10.1109/ted.2019.2901668
Publikováno v:
IEEE Transactions on Electron Devices. 65:4238-4244
In advanced technology nodes, an increase in power density, use of nonplanar architectures, and novel materials can aggravate local self-heating due to active power dissipation. In this paper, 3-D device simulations are performed to analyze thermal e
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ee01781e06d03232a42ff2c5fe1081f1
https://doi.org/10.1109/ted.2018.2863730
https://doi.org/10.1109/ted.2018.2863730
Publikováno v:
IEEE Transactions on Electron Devices. 65:3654-3661
Parameter variations in the transistor characteristics with new materials and process steps pose an increasing challenge for CMOS scaling to nanometer feature size. Alternate channel materials such as silicon–germanium (SiGe) for p-type field effec
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3acdd7ef266a0714ba2af718673cb251
https://doi.org/10.1109/ted.2018.2858748
https://doi.org/10.1109/ted.2018.2858748
Publikováno v:
IEEE Transactions on Electron Devices. 65:3548-3554
Vertically stacked junctionless accumulation mode (JLAM) nanowire field effect transistors (NWFETs) outperform inversion-mode (IM) NWFETs below 10-nm technology nodes, but the vertical stacking of nanowires (NWs) has a constraint of position dependen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9d3b0b93e9b97e3ccbeecb7de66ccd6f
https://doi.org/10.1109/ted.2018.2845541
https://doi.org/10.1109/ted.2018.2845541
Autor:
S. S. Parihar, Kritika Aditya, Ramendra Singh, Terence B. Hook, Yogesh Singh Chauhan, Abhisek Dixit, Reinaldo A. Vega
Publikováno v:
IEEE Electron Device Letters. 39:1246-1249
In this letter, we have investigated the RF performance of a negative capacitance FinFET (NC-FinFET) using BSIM-CMG compact model extracted from DC and RF measured data of 10-nm technology node devices. This physics-based RF model is then coupled sel
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a6c7ce7e5dae3898743e305cf0301cac
https://doi.org/10.1109/led.2018.2846026
https://doi.org/10.1109/led.2018.2846026
Publikováno v:
IEEE Transactions on Electron Devices. 65:1246-1252
Nanowire field-effect transistors (NWFETs) have emerged as promising candidates for realization of advanced CMOS technology nodes. Due to small nanowire dimensions, NWFETs are vulnerable to the impact of process-induced random local variations, such
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2f005e6eb373e69eb4fefceef7fb4522
https://doi.org/10.1109/ted.2018.2797799
https://doi.org/10.1109/ted.2018.2797799
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 6, Pp 551-556 (2018)
In this paper, we propose the extendibility of ultra-thin body and box (UTBB) devices to 7 and 5 nm technology nodes focusing on electrostatics. A difficulty in scaling traditional UTBB is the need for SOI scaling to about one fourth of the gate leng
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::deb917a448cfe8add7cd6eca803168b5
https://ieeexplore.ieee.org/document/8302502/
https://ieeexplore.ieee.org/document/8302502/
Publikováno v:
IEEE Transactions on Electron Devices. 64:5274-5278
An analytical model of parasitic capacitance in inserted-oxide FinFETs (iFinFETs) is proposed. A comparative study on the parasitic capacitance of contemporary multigate devices conforming to 7-nm technology node targets is presented. The proposed mo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a8604b8f9e1f598cc3f9b47ad57008d8
https://doi.org/10.1109/ted.2017.2761984
https://doi.org/10.1109/ted.2017.2761984