Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Tejas Karkhanis"'
Publikováno v:
ACM Transactions on Computer Systems. 27:1-37
A mechanistic model for out-of-order superscalar processors is developed and then applied to the study of microarchitecture resource scaling. The model divides execution time into intervals separated by disruptive miss events such as branch mispredic
Publikováno v:
IEEE Micro. 27:84-93
Software developers can gain insight into software-hardware interactions by decomposing processor performance into individual cycles-per-instruction components that differentiate cycles consumed in active computation from those spent handling various
Publikováno v:
ASPLOS
A common way of representing processor performance is to use Cycles per Instruction (CPI) `stacks' which break performance into a baseline CPI plus a number of individual miss event CPI components. CPI stacks can be very helpful in gaining insight in
Publikováno v:
HPCA
Business text analytics applications have seen rapid growth, driven by the mining of data for various decision making processes. Regular expression processing is an important component of these applications, consuming as much as 50% of their total ex
Autor:
James E. Smith, Tejas Karkhanis
Publikováno v:
ISCA
Automated design of superscalar processors can provide future system-on-chip (SOC) designers with a turn-key method of generating superscalar processors that are Pareto-optimal in terms of performance, energy consumption, and area for the target appl
Autor:
Carlos Costa, Carlo Bertolli, Yoonho Park, Patrick Siegl, Tong Chen, Arpith C. Jacob, Changhoan Kim, Philip Jacob, John Kevin Patrick O'Brien, Daniel A. Prener, Constantinos Evangelinos, Diego Sanchez Gallo, Jose R. Brunheroto, Pradip Bose, Samuel Antao, Martin Ohmacht, Chen-Yong Cher, J. Doi, Bruce M. Fleischer, Ravi Nair, Olivier Sallenave, Thomas W. Fox, John A. Gunnels, Leopold Grinberg, Hans M. Jacobson, Jaime H. Moreno, Kyung Dong Ryu, Bryan S. Rosenburg, Zehra Sura, Tejas Karkhanis, Mauricio J. Serrano, Krishnan Sugavanam
Publikováno v:
IBM Journal of Research and Development. 59:17:1-17:14
Many studies point to the difficulty of scaling existing computer architectures to meet the needs of an exascale system (i.e., capable of executing $10^{18} $ floating-point operations per second), consuming no more than 20 MW in power, by around the
Autor:
James Wilson Bishop, Kimberly Marie Fernsler, Hung Qui Le, Markus Kaltenbach, Dung Quoc Nguyen, David Stephen Levitan, Brian R. Konigsburg, Richard J. Eickemeyer, Mary D. Brown, J. A. Van Norstrand, S. Tung, Balaram Sinharoy, José E. Moreira, Michael K. Gschwind, Tejas Karkhanis, David A. Hrusecky, Maarten J. Boersma, Jentje Leenstra, Michael Kroener, Kenneth L. Ward
Publikováno v:
IBM Journal of Research and Development. 59:2:1-2:21
The POWER8™ processor is the latest RISC (Reduced Instruction Set Computer) microprocessor from IBM. It is fabricated using the company's 22-nm Silicon on Insulator (SOI) technology with 15 layers of metal, and it has been designed to significantly
Publikováno v:
ISCA
Front-end instruction delivery accounts for a significant fraction of the energy consumed in a dynamic superscalar processor. The issue queue in these processors serves two crucial roles: it bridges the front and back ends of the processor and serves
Autor:
James E. Smith, Michael K. Gschwind, Pradip Bose, Hans M. Jacobson, Alper Buyuktosunoglu, Sandhya Dwarkadas, Philip G. Emma, K. Das, David H. Albonesi, Victor Zyuban, Peter W. Cook, Tejas Karkhanis, V. Srinivasan, Prabhakar Kudva, Stanley E. Schuster, David Brooks
Publikováno v:
Power-Aware Computer Systems ISBN: 9783540010289
PACS
PACS
We present the high-level microarchitecture of LPX: a low-power issue-execute processor prototype that is being designed by a joint industry-academia research team. LPX implements a very small subset of a RISC architecture, with a primary focus on a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6b68a67c27e18ab7d6ec7962aac1b46c
https://doi.org/10.1007/3-540-36612-1_1
https://doi.org/10.1007/3-540-36612-1_1
Publikováno v:
ISLPED
Just-In-Time instruction delivery is a general method for saving energy in a microprocessor by dynamically limiting the number of in-flight instructions. The goal is to save energy by (1) fetching valid instructions no sooner than necessary, avoiding