Zobrazeno 1 - 3
of 3
pro vyhledávání: '"Teiji Yutaka"'
Autor:
Nobuhiro Ide, T. Okada, Fujio Ishihara, M. Suzuoki, Hiroaki Murakami, Akio Ohba, Toshinori Sato, Masaaki Oka, Atsushi Kunimatsu, Yukio Endo, Teiji Yutaka, M. Hirano, Haruyuki Tago, T. Kamei
Publikováno v:
IEEE Micro. 20:40-47
Two vector units embedded in the emotion engine chip support high-quality 3D graphics, emotion synthesis, and 300-MHz, 5.5-GFLOPS operation for the recently introduced PlayStation2 game entertainment system.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::46d2f5c9b60b4bfec73aaf0324dc1cad
https://doi.org/10.1109/40.848471
https://doi.org/10.1109/40.848471
Autor:
Akira Aono, Hiroaki Murakami, Toshiyuki Hiroi, Nobuhiro Ide, T. Okada, Masaaki Oka, Y. Ohtaguro, S. Okamoto, Yukihiro Urakawa, K. Hashimoto, M. Suzuoki, Akio Ohba, Teiji Yutaka, Atsushi Kunimatsu, Ken Kutaragi, H. Magoshi, Yasuyuki Yamamoto, H. Goto, Masato Nagamatsu, M. Funyu, Masayoshi Tanaka, M. Furuhashi
Publikováno v:
IEEE Journal of Solid-State Circuits. 34:1608-1618
A 250-MHz microprocessor intended for home computer entertainment consists of a CPU core with 128-b multimedia extensions, two single-instruction, multiple-data (SIMD) very long instruction word (VLIW) vector processors containing ten floating-point
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9ae14e7db5651b5a67fd21374c47d30f
https://doi.org/10.1109/4.799870
https://doi.org/10.1109/4.799870
Autor:
S. Yoshioka, M. Suzuoki, T. Teruyama, Yasuyuki Yamamoto, Toshiyuki Hiroi, T. Yoshida, Howard A. Landman, T. Kobayashi, T. Sakamoto, R. Agarwal, Y. Fujimoto, H. Tago, K. Malik, Akio Ohba, Teiji Yutaka, Masaaki Oka, F.M. Raam
Publikováno v:
1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).
This 250 MHz 2-way superscalar MIPS-compatible embedded microprocessor is targeted for use in high-end consumer electronics, game, and network markets. The microprocessor features a high-bandwidth (2.0 GB/s peak) 128 b external bus. Internal datapath
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::94d0858cf587de344930af8e445a326b
https://doi.org/10.1109/isscc.1999.759231
https://doi.org/10.1109/isscc.1999.759231