Zobrazeno 1 - 10
of 25
pro vyhledávání: '"Tawfiq Musah"'
Publikováno v:
IEEE Access, Vol 12, Pp 148281-148293 (2024)
This paper proposes a new modulation-driven pipelining approach for reducing the complexity of speculative decision feedback equalizers (DFEs). The scalable receiver architecture enables the detection and equalization of multiple pulse amplitude modu
Externí odkaz:
https://doaj.org/article/5019d416d4214d69976ac45d74b87f96
Autor:
Sydney Lang, Tawfiq Musah
Publikováno v:
IEEE Access, Vol 12, Pp 810-823 (2024)
This paper proposes a new authentication approach targeted to wireline broadcast communication systems for automotive and industrial applications. The proposed approach leverages jitter amplification in wireline channels, that become stronger feature
Externí odkaz:
https://doaj.org/article/a4fed95620864485a25730aa0fe98153
Publikováno v:
IEEE Open Journal of Circuits and Systems, Vol 4, Pp 324-335 (2023)
This paper proposes a hybrid phase detector for use in multilevel timing recovery systems. The proposed approach suppresses errant zero-crossings associated with multilevel baud rate phase detectors and ensures maximum signal swing in lock, with mini
Externí odkaz:
https://doaj.org/article/0c1a2d3458964d59a1bcc111309922e0
Autor:
Ahmed Abdelaziz, Tawfiq Musah
Publikováno v:
Electronics Letters, Vol 58, Iss 14, Pp 542-544 (2022)
Abstract This letter presents a novel time latch for high speed time domain analogue to digital converters. The time latches reported in literature suffer from a limited maximum operating frequency, which makes them unsuitable for high frequency appl
Externí odkaz:
https://doaj.org/article/6aab85c09ac44fe7b93884e0029ec67e
Autor:
Abishek Namachivayam, Tawfiq Musah
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 69:3927-3939
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bee9cbbb6073a5c3503980d1ff5c64d5
https://doi.org/10.1109/tcsi.2022.3191740
https://doi.org/10.1109/tcsi.2022.3191740
This article presents a time domain multiply-and-accumulate (MAC) engine used for convolutional neural networks. Time domain is chosen for efficiency as it allows for compact representation of multi-bit inputs on a single wire. This reduces gate coun
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::52d98052a654d4737fe4fe0e17e445c5
https://doi.org/10.22541/au.167710265.55273622/v1
https://doi.org/10.22541/au.167710265.55273622/v1
Autor:
Mohamed O. Abouzeid, Tawfiq Musah
Publikováno v:
Microelectronics Journal. :105835
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::590abc70bea317606d9cfa8f19b919b3
https://doi.org/10.1016/j.mejo.2023.105835
https://doi.org/10.1016/j.mejo.2023.105835
Autor:
Mohamed Ahmed, Tawfiq Musah
Publikováno v:
2022 IEEE International Symposium on Circuits and Systems (ISCAS).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c33bcd2e089f71684638ff3c764bc3db
https://doi.org/10.1109/iscas48785.2022.9937506
https://doi.org/10.1109/iscas48785.2022.9937506
Autor:
Ahmed Ahmed Abdelaziz, Tawfiq Musah
Publikováno v:
ISCAS
This paper does an empirical investigation of the effect of nonlinearity in time-based wireline receivers. The linearity of the voltage-to-time converter (VTC), a necessary component of the time-based receiver is simulated, and its impact on the perf
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::197d16797e695dc491543a81064c5119
https://doi.org/10.1109/iscas51556.2021.9401516
https://doi.org/10.1109/iscas51556.2021.9401516
Autor:
Mozhgan Mansuri, Sudip Shekhar, Clark Roberts, Sami Hyvonen, R. Mooney, Ganesh Balamurugan, James E. Jaussi, Shreyas Sen, Rajesh Inti, Gokce Keskin, Bryan K. Casper, Tawfiq Musah, Bryce D. Horine, Joseph T. Kennedy, Michael W. Leddige, Tzu-Chien Hsueh
Publikováno v:
IEEE Journal of Solid-State Circuits. 49:3079-3090
This paper details the design of an 8-lane bidirectional link for both within-the-box and external communications in 22 nm CMOS technology. A low profile connector with a high density cable assembly ensure a data rate of up to 32 Gb/s per lane while
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d9a551e127f5949e6caf56332b490156
https://doi.org/10.1109/jssc.2014.2348556
https://doi.org/10.1109/jssc.2014.2348556