Zobrazeno 1 - 2
of 2
pro vyhledávání: '"Tatsuo Kasaoka"'
Autor:
H. Matsuoka, Atsushi Hachisuka, Hideyuki Noda, K. Shigeta, Kenji Anami, Fukashi Morishita, Isamu Hayashi, A. Amo, M. Niiro, M. Okamoto, T. Gyohten, Tatsuo Kasaoka, Katsumi Dosaka, K. Takahashi, Kazutami Arimoto, H. Shinkawata, T. Yoshihara, K. Fujishima
Publikováno v:
IEEE Journal of Solid-State Circuits. 40:204-212
An embedded DRAM macro with a self-adjustable timing control (STC) scheme, a negative edge transmission scheme (NET), and a power-down data retention (PDDR) mode is developed. A 13.98-mm/sup 2/ 16-Mb embedded DRAM macro is fabricated in 0.13 /spl mu/
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::31bb5c834b4cc5e50f645e3bcab987de
https://doi.org/10.1109/jssc.2004.837986
https://doi.org/10.1109/jssc.2004.837986
Autor:
H. Matsuoka, M. Okamoto, A. Amo, K. Takahashi, Isamu Hayashi, Kazutami Arimoto, Katsumi Dosaka, Tatsuo Kasaoka, Atsushi Hachisuka, K. Shigeta, M. Niiro, Fukashi Morishita, T. Gyohten, H. Shinkawata
Publikováno v:
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
An embedded DRAM macro with self-adjustable timing control and a power-down data retention scheme is described. A 16Mb test chip is fabricated in a 0.13/spl mu/m low-power process and it achieves 312MHz random cycle operation. Data retention power is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8d207d19b5590605443348544d0f08fc
https://doi.org/10.1109/isscc.2004.1332664
https://doi.org/10.1109/isscc.2004.1332664