Zobrazeno 1 - 10
of 23
pro vyhledávání: '"Tatjana R. Nikolic"'
Publikováno v:
ETRI Journal, Vol 43, Iss 3, Pp 471-482 (2020)
Several code‐division multiple access (CDMA)‐based interconnect schemes have been recently proposed as alternatives to the conventional time‐division multiplexing bus in multicore systems‐on‐chip. CDMA systems with a dynamic assignment of s
Externí odkaz:
https://doaj.org/article/fe19c4fc7cb94e7584e2828ff98852ab
Publikováno v:
2022 57th International Scientific Conference on Information, Communication and Energy Systems and Technologies (ICEST).
Publikováno v:
2022 57th International Scientific Conference on Information, Communication and Energy Systems and Technologies (ICEST).
Publikováno v:
2019 IEEE 31st International Conference on Microelectronics (MIEL).
Performance of real-time digital signal processing systems is limited by their data computing capability. Therefore, evaluation of different architectures to determine the most efficient one is an important task. An efficient architecture for the imp
Autor:
Milica D. Jovanovic, Igor Stojanovic, Tatjana R. Nikolic, Sandra M. Djosic, Goran Lj. Djordjevic
Publikováno v:
Expert Systems with Applications. 167:114188
Among the numerous radio-based solutions for indoor localization, ultra-wideband (UWB) technology is of particular interest due to its signal characteristics. The wide bandwidth of the UWB signal provides a fine time resolution of the transmitted pul
Publikováno v:
Microelectronics Journal. 106:104923
CDMA based on-chip interconnects have recently drawn attention due to lower variance of data transfer latency compared with the shared-bus. In this paper, we present a novel design of CDMA bus arbitration unit, which allocates codewords to system nod
Publikováno v:
The Journal of Supercomputing. 72:275-294
Shrinking technology and growing complexity of the contemporary system on chip designs require high performance and reliable interconnection architecture. Binary CDMA on-chip bus permits simultaneous use of the shared communication medium by multiple
Publikováno v:
Microelectronics Reliability. 55:272-281
High computing capabilities and limited number of input/output pins of modern integrated circuits require an efficient and reliable interconnection architecture. The proposed communication scheme allows a large number of IP cores to send data over a
Publikováno v:
2017 IEEE 30th International Conference on Microelectronics (MIEL).
Wireless sensor networks (WSNs) include a large number of distributed sensor nodes that consist of sensor, microcontroller and transceiver block. As the main source of energy sensor nodes usually use non-rechargeable batteries, so that the stored ene
Publikováno v:
Advances in Electrical and Computer Engineering, Vol 14, Iss 1, Pp 37-42 (2014)
This paper presents architecture for matrix multiplication optimized to be integrated as an accelerator unit to a host computer. Two linear systolic arrays with unidirectional data flow (ULSA), used as hardware accelerators, where synthesized in this