Zobrazeno 1 - 10
of 21
pro vyhledávání: '"Tat-Kwan Yu"'
Publikováno v:
Thin Solid Films. 253:508-512
Tungsten plug contacts/vias electromigration experiments have been performed using a variety of test structures under different stress conditions. It was found that electromigration failures, failure mechanisms of tungsten plug contacts/vias, were st
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::855acf6c94991db16febf7ff72e693e2
https://doi.org/10.1016/0040-6090(94)90375-1
https://doi.org/10.1016/0040-6090(94)90375-1
Publikováno v:
International Journal of Circuit Theory and Applications. 19:579-592
A major bottleneck in the design and parametric yield optimization of CMOS integrated circuits lies in the high cost of the circuit simulations. One method that significantly reduces the simulation cost is to approximate the circuit performances by f
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f55d44f10419805821203c23782f446e
https://doi.org/10.1002/cta.4490190606
https://doi.org/10.1002/cta.4490190606
Publikováno v:
Journal of Quality Technology. 22:15-22
Taguchi's off-line quality control methods for product and process improvement emphasize experiments to design quality "into" products and processes. In Very Large Scale Integrated (VLSI) circuit design, the application of interest here, compu..
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ed0644c5ffa86512301f9e7be903dbb7
https://doi.org/10.1080/00224065.1990.11979201
https://doi.org/10.1080/00224065.1990.11979201
Publikováno v:
International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).
This paper presents a new two-dimensional (2-D) low pass filter model for the prediction of post-chemical-mechanical polishing (CMP) die level wafer topography variation caused by the interconnect metal density of a circuit layout. It is demonstrated
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::49eab1a87286a8d9f6fe4fd3a6044b18
https://doi.org/10.1109/iedm.1999.824296
https://doi.org/10.1109/iedm.1999.824296
Publikováno v:
ICCAD
A method for parametric yield optimization which significantly reduces the simulation cost is proposed. The method assumes that the circuit performances ultimately determining yield can be approximated by computationally inexpensive functions of the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3bf3b4e6e2bd96e87a62712a52778a64
https://doi.org/10.1109/iccad.1989.76933
https://doi.org/10.1109/iccad.1989.76933
Publikováno v:
Proceedings of IEEE International Electron Devices Meeting.
Chemical mechanical polishing (CMP) has emerged as a critical technology for advanced integrated circuit fabrication. This paper presents for the first time a physical CMP model that includes the effects of polishing pad roughness and dynamic interac
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9de3e2d9101a4d47f5017c70f8dc0c73
https://doi.org/10.1109/iedm.1993.347263
https://doi.org/10.1109/iedm.1993.347263
Publikováno v:
Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit.
A new low voltage flash circuit model is presented. This SPICE model is used to identify techniques for reducing the average power dissipated in a flash memory during a programming cycle. The AND flash memory cell is used in this analysis. For a sele
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3bf625f3da4bdbbf6030ba3ed6f8a368
https://doi.org/10.1109/asic.1996.552016
https://doi.org/10.1109/asic.1996.552016
Publikováno v:
Proceedings of International Workshop on Numerical Modeling of processes and Devices for Integrated Circuits: NUPAD V.
This paper presents, for the first time, a physical model of chemical-mechanical polishing (CMP) that combine the effects of polishing pad roughness and slurry hydrodynamic pressure. Recently, the authors introduced a statistical asperity model to an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::440108806d79ceaf2e8964a80ad43d1f
https://doi.org/10.1109/nupad.1994.343498
https://doi.org/10.1109/nupad.1994.343498
Publikováno v:
Proceedings of 1994 IEEE International Electron Devices Meeting.
A CAD EEPROM circuit model is essential to the design/optimization of low power non-volatile memory products. This paper presents a new FETMOS EEPROM circuit model that includes both Fowler-Nordheim and band-to-band tunneling. A DC model for FETMOS o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1ec4f71fc83d2168c43ac713a04d91e3
https://doi.org/10.1109/iedm.1994.383441
https://doi.org/10.1109/iedm.1994.383441
Publikováno v:
International Electron Devices Meeting 1991 [Technical Digest].
A combined approach to the modeling of selective epitaxial silicon growth (SEG) is presented. The simulations consider the following effects: reactor fluid dynamics, gas chemistry, mass transport in the stagnant layer, and device profile evolution. R
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e59e5be3011983f074c0919eeeb7aac3
https://doi.org/10.1109/iedm.1991.235285
https://doi.org/10.1109/iedm.1991.235285