Výsledky vyhledávání - "Taras Iakymchuk"

Akademický článek

A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks

Autor: Leandro D. Medus, Taras Iakymchuk, Jose Vicente Frances-Villora, Manuel Bataller-Mompean, Alfredo Rosado-Munoz

Publikováno v: IEEE Access, Vol 7, Pp 76084-76103 (2019)

New chips for machine learning applications appear, they are tuned for a specific topology, being efficient by using highly parallel designs at the cost of high power or large complex devices. However, the computational demands of deep neural network

Externí odkaz: https://doaj.org/article/3025a9b91ab74687b078d3109097f600

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Akademický článek

Novel Resistance Measurement Method: Analysis of Accuracy and Thermal Dependence with Applications in Fiber Materials

Autor: Silvia Casans, Alfredo Rosado-Muñoz, Taras Iakymchuk

Publikováno v: Sensors, Vol 16, Iss 12, p 2129 (2016)

Material resistance is important since different physicochemical properties can be extracted from it. This work describes a novel resistance measurement method valid for a wide range of resistance values up to 100 GΩ at a low powered, small sized, d

Externí odkaz: https://doaj.org/article/310bd8d509c540c89b099adef1da7df3

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A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks

Autor: Jose V. Frances-Villora, Leandro D. Medus, Manuel Bataller-Mompeán, Taras Iakymchuk, Alfredo Rosado-Muñoz

Publikováno v: IEEE Access, Vol 7, Pp 76084-76103 (2019)
Medus, Leandro Daniel Iakymchuk, Taras Francés Villora, José Vicente Bataller Mompean, Manuel Rosado Muñoz, Alfredo 2019 A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks Ieee Access 7 76084 76103
RODERIC. Repositorio Institucional de la Universitat de Valéncia
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Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6b72f5531fa1c5b3f2b6fa59c212b372
https://ieeexplore.ieee.org/document/8731886/

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High resistance measurement circuit for fiber materials: Application to moisture content estimation

Autor: Taras Iakymchuk, S. Casans, Alfredo Rosado-Muñoz

Publikováno v: Measurement. 119:167-174

Measuring very high resistance values is a difficult task since low voltage or currents are present and thus, noise and amplification must be carefully done, especially when low resistance values are required to be measured using the same circuit, to

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::c171ff3c00e27e9a070726ed0661da75
https://doi.org/10.1016/j.measurement.2018.01.072

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POWERLINK and Ethernet/IP Comparison as Robust Industrial Ethernet Protocols

Autor: Taras Iakymchuk, Marcos García-Chulbi, Alfredo Rosado-Muñoz, Juan Barrios-Aviles

Publikováno v: IFAC-PapersOnLine. 50:363-368

Industrial protocols based on Ethernet are common in automation and control systems nowadays. As different protocols claim the advantages over competitors based on their own experimental results, it is necessary to perform independent analyses where

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a54a00b0e9fc08a5daebcf94e256eb2e
https://doi.org/10.1016/j.ifacol.2017.08.159

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An Scalable matrix computing unit architecture for FPGA and SCUMO user design interface

Autor: Manuel Bataller-Mompeán, Taras Iakymchuk, Alfredo Rosado-Muñoz, Asgar Abbaszadeh, Jose V. Frances-Villora

Publikováno v: Abbaszadeh, Asgar Iakymchuk, Taras Bataller Mompean, Manuel Francés Villora, José Vicente Rosado Muñoz, Alfredo 2019 An Scalable matrix computing unit architecture for FPGA and SCUMO user design interface Electronics 8 1 94-1 94-20
RODERIC. Repositorio Institucional de la Universitat de Valéncia
instname
Electronics
Volume 8
Issue 1
Electronics, Vol 8, Iss 1, p 94 (2019)

High dimensional matrix algebra is essential in numerous signal processing and machine learning algorithms. This work describes a scalable square matrix-computing unit designed on the basis of circulant matrices. It optimizes data flow for the comput

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::bb0491dd6d8ee3879779e1e310278171
https://doi.org/10.3390/electronics8010094

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Versatile Direct and Transpose Matrix Multiplication with Chained Operations: An Optimized Architecture Using Circulant Matrices

Autor: José V. Francés Villora, Emmanuel Ovie Osimiry, Taras Iakymchuk, Alfredo Rosado-Muñoz, Manuel Bataller Mompean

Publikováno v: IEEE Transactions on Computers. 65:3470-3479

With growing demands in real-time control, classification or prediction, algorithms become more complex while low power and small size devices are required. Matrix multiplication (direct or transpose) is common for such computation algorithms. In num

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::9e3367c2fcb939eb75f23c0be753e77c
https://doi.org/10.1109/tc.2016.2538235

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On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems

Autor: Luis A. Plana, A. Rosado, Teresa Serrano-Gotarredona, Alejandro Linares-Barranco, Amirreza Yousefzadeh, Steve Temple, Bernabe Linares-Barranco, Taras Iakymchuk, Steve Furber, Miroslaw Jablonski

Publikováno v: idUS. Depósito de Investigación de la Universidad de Sevilla
instname
IEEE Transactions on Biomedical Circuits and Systems
Digital.CSIC. Repositorio Institucional del CSIC
Yousefzadeh, A, Jabłoński, M, Iakymchuk, T, Linares-Barranco, A, Rosado, A, Plana, L A, Temple, S, Serrano-Gotarredona, T, Furber, S & Linares-Barranco, B 2017, ' On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems ', IEEE Transactions on Biomedical Circuits and Systems, vol. 11, no. 5, pp. 1-15 . https://doi.org/10.1109/TBCAS.2017.2717341

Address event representation (AER) is a widely employed asynchronous technique for interchanging “neural spikes” between different hardware elements in neuromorphic systems. Each neuron or cell in a chip or a system is assigned an address (or ID)

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::29192267da8bcc3442181a840d48fa2b

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Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems

Autor: Bernabe Linares-Barranco, Luis A. Plana, Alejandro Linares-Barranco, Teresa Serrano-Gotarredona, Taras Iakymchuk, Steve Furber, A. Rosado, Miroslaw Jablonski, Amirreza Yousefzadeh

Publikováno v: Digital.CSIC. Repositorio Institucional del CSIC
instname
ISCAS
2017 IEEE International Symposium on Circuits and Systems (ISCAS)
Yousefzadeh, A, Jabłoński, M, Iakymchuk, T, Linares-Barranco, A, Rosado, A, Plana, L A, Serrano-Gotarredona, T, Furber, S & Linares-Barranco, B 2017, Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems . in 2017 IEEE International Symposium on Circuits and Systems (ISCAS) . IEEE . https://doi.org/10.1109/ISCAS.2017.8050802
idUS. Depósito de Investigación de la Universidad de Sevilla

Paper presented at the 2017 IEEE International Symposium on Circuits and Systems (ISCAS), held in Baltimore, MD, USA, on 28-31 May 2017.
We propose demonstration of a serial link for fast asynchronous communication in massively parallel platform

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::b7813aadd029aa42cffc7eba5169fa3d
http://hdl.handle.net/10261/195596

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