Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Tapobrata Bandyopadhyay"'
Autor:
Kevin Scholz, S M Stalin, Robert DeMoor, Tapobrata Bandyopadhyay, Snehamay Sinha, Shriram D. Moharil
Publikováno v:
2017 IEEE 21st Workshop on Signal and Power Integrity (SPI).
This paper presents a case study of DDR3 interface timing jitter of a DDR subsystem on an evaluation module. The total jitter was separated into various Signal Integrity (SI) and Power Integrity (PI) effects, including signal crosstalk, impedance dis
Publikováno v:
2016 IEEE Dallas Circuits and Systems Conference (DCAS).
Skew matching in high speed interfaces is achieved through the use of serpentine structures both in the board and in the package substrate. The basic assumption is that length matching through the use of the serpentine structures will enable delay sk
Autor:
Tom Johnson, Thomas Krause, Anita Pratti, Snehamay Sinha, Bill Taboada, Tapobrata Bandyopadhyay
Publikováno v:
2016 IEEE 66th Electronic Components and Technology Conference (ECTC).
System co-design techniques are essential in ensuring good package and PCB designs that satisfies the signal and power integrity requirements of a system. This paper focuses on improving system-level signal integrity of high-speed serial links in hig
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 2:1426-1433
Interconnecting integrated circuits (ICs) and 3-D-ICs to the system board (printed circuit board) are currently achieved using organic or silicon-based interposers. Organic interposers face several challenges in packaging 2-D and 3-D-ICs beyond the 3
Autor:
Tapobrata Bandyopadhyay, Ki Jin Han, Ritwik Chatterjee, Madhavan Swaminathan, Daehyun Chung, Rao Tummala
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 1:893-903
3-D integration of microelectronic systems reduces the interconnect length, wiring delay, and system size, while enhancing functionality by heterogeneous integration. Through silicon via (TSV) is a key building block for high-performance 3-D systems.
Publikováno v:
IEEE Transactions on Advanced Packaging. 33:804-817
This paper proposes an efficient method to model through-silicon via (TSV) interconnections, an essential building block for the realization of silicon-based 3-D systems. The proposed method results in equivalent network parameters that include the c
Autor:
Toshihiko Jimbo, Kiyoshige Kojima, Venky Sundaram, Vivek Sridharan, Fuhan Liu, Rao Tummala, Tapobrata Bandyopadhyay, Naomi Shiga
Publikováno v:
International Symposium on Microelectronics. 2010:000836-000841
In this paper, we present a novel high density high performance ultra-thin organic laminate, X-R-1, with low cost standard PCB fabrication processes for RF and high frequency applications. The X-R-1 substrate, developed at Zeon Corporation is a new g
Publikováno v:
IEEE Microwave and Wireless Components Letters. 21:598-600
A novel double sided silicon interposer for low impedance power delivery is presented. In this letter, a model for power ground planes in inhomogeneous dielectrics with conductive subsections using the multi-layered finite difference method (M-FDM) i
Autor:
Vijay Sukumaran, Rao Tummala, Venky Sundaram, Tapobrata Bandyopadhyay, Sung Kyu Lim, Gokul Kumar
Publikováno v:
2011 IEEE 61st Electronic Components and Technology Conference (ECTC).
Smart mobile applications are driving the demand for higher logic-to-memory bandwidth (BW) in 10–30 GB/s range with lower power consumption and larger memory capacity. This paper presents a radically-different, scalable and lower cost approach than
Autor:
Qiao Chen, Vijay Sukumaran, Nitesh Kumbhat, Choukri Karoui, Kenji Kitaoka, Tapobrata Bandyopadhyay, Motoshi Ono, Yoichiro Sato, Madhavan Swaminathan, Christian Nopper, Mitsuru Watanabe, Venky Sundaram, Fuhan Liu, R.V. Pucha, Rao Tummala, Yuya Suzuki
Publikováno v:
2011 IEEE 61st Electronic Components and Technology Conference (ECTC).
This paper demonstrates thin glass interposers with fine pitch through package vias (TPV) as a low cost and high I/O substrate for 3D integration. Interposers for packaging of ULK and 3D-ICs need to support large numbers of die to die interconnection