Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Tanusree Kaibartta"'
Publikováno v:
IEEE Access, Vol 9, Pp 160987-161002 (2021)
Demand for small, multi-functional, high performance electronic product with less power consumption is increasing rapidly. To meet the demand, IC design has been shifted from two dimensional integrated circuit (2D-IC) to three dimensional integrated
Externí odkaz:
https://doaj.org/article/d8b395778c994c2bac4854483f46f85e
Publikováno v:
Journal of Electronic Testing. 36:239-253
In 3D IC, wrapper chains can span across vertical directions which causes the increase in number of TSVs(through-silicon-vias)(which is used to interconnect different cores in the vertical directions). Excessive use of TSVs in wrapper design causes r
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f8dd2d1607ebd3c918829ab3bcb8eb3c
https://doi.org/10.1007/s10836-020-05872-7
https://doi.org/10.1007/s10836-020-05872-7
Publikováno v:
IET Computers & Digital Techniques. 13:383-396
The interconnect between the cores of System-on-Chip (SOC) degrades the circuit performance by contributing to circuit delay and power consumption. To reduce this problem, SOC-based three-dimensional (3D) integrated circuit (IC) technology as a promi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f15687aa11e99620ef24463e6a736e16
https://doi.org/10.1049/iet-cdt.2018.5079
https://doi.org/10.1049/iet-cdt.2018.5079
Publikováno v:
ATS
The possibility of 3D integrated circuit (3D IC) has been considered as a choice to overcome the difficulties faced by two-dimensional integrated circuits (2D IC). Several technologies exist to connect the layers in 3D IC. Among these technologies th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2cc47dfe35e1142442da61257697105b
https://doi.org/10.1109/ats49688.2020.9301580
https://doi.org/10.1109/ats49688.2020.9301580
Publikováno v:
International Journal of VLSI & Signal Processing. 5:1-10
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f88df514b1a86621333ec18d14b812c0
https://doi.org/10.14445/23942584/ijvsp-v5i3p101
https://doi.org/10.14445/23942584/ijvsp-v5i3p101
Autor:
Debesh K. Das, Tanusree Kaibartta
Publikováno v:
Communications in Computer and Information Science ISBN: 9789811359491
VDAT
VDAT
Core of an integrated circuit is supplied test stimulus generated by an external test source and then responses of the core are compared with expected responses. Test access mechanism (TAM) is a mechanism responsible for transporting test data to the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4eea2fe70581e49da03a1a6c16369360
https://doi.org/10.1007/978-981-13-5950-7_27
https://doi.org/10.1007/978-981-13-5950-7_27
Autor:
Debesh K. Das, Tanusree Kaibartta
Publikováno v:
IDT
System-on-a-chip (SOC) uses embedded cores those require a test access architecture called Test Access Mechanism (TAM) to access the cores for the purpose of testing. Optimization of TAM and test time at SOC level is an important area of research. Ho
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0a9d1626b3a9689a244f5fe03ff6b4c9
https://doi.org/10.1109/idt.2015.7396746
https://doi.org/10.1109/idt.2015.7396746
Publikováno v:
2015 6th Asia Symposium on Quality Electronic Design (ASQED).
System-on-a-chip (SOC) uses embedded cores that require a test access architecture called Test Access Mechanism (TAM) to access the cores for the purpose of testing. This approach can be used for testing of three dimensional stacked integrated circui
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::80bade7aed6c392268bcc869aeddd523
https://doi.org/10.1109/acqed.2015.7274008
https://doi.org/10.1109/acqed.2015.7274008