Zobrazeno 1 - 10 of 38 pro vyhledávání: '"Takuji, Miki"'
3
In-Place Evaluation of Powering and Signaling Within Fan-Out Multiple IC Chip Packaging
Autor: Hiroki Sonoda, Ryo Kasai, Daisuke Tanaka, Yoshihide Murakami, Kyoshi Mihara, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Takuji Miki, Makoto Nagata
Publikováno v: IEEE Transactions on Components, Packaging and Manufacturing Technology. 12:1140-1149
This article confirms the advantage of fan-out (FO) packaging in the electrical performance of power delivery among integrated circuit (IC) chips with the best use of land side capacitors (LSCs). On-chip in-place waveform measurements quantitatively
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::491ea5bf15b07f40f38048e11359ae75
https://doi.org/10.1109/tcpmt.2022.3179149
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4
Physical Attack Protection Techniques for IC Chip Level Hardware Security
Autor: Noriyuki Miura, Makoto Nagata, Takuji Miki
Publikováno v: IEEE Transactions On Very Large Scale Integration (VLSI) Systems. 30(1):5-14
Secure hardware systems are threatened by adversarial attempts on integrated circuit (IC) chips in a practical utilization environment. This article provides overviews of physical attacks on cryptographic circuits, associated vulnerabilities in an IC
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::af6f59db0cd879fbc24b3c2447df5cdf
http://www.lib.kobe-u.ac.jp/handle_kernel/90008959
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8
Testing Embedded Toggle Generation Through On-Chip IR-Drop Measurements
Autor: Kazuki Monta, Leonidas Katselas, Ferenc Fodor, Takuji Miki, Alkis Hatzopoulos, Makoto Nagata, Erik Jan Marinissen
Publikováno v: IEEE Design & Test, 39(5), 79-87. Institute of Electrical and Electronics Engineers
Editor's notes: The authors present an IR-drop-based power-domain-scenario-based test methodology along with an in-field diagnosis technique. This utilizes on-chip monitor (OCM) circuits, and the toggle patterns can be designed with test pattern gene
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7decae184fda811e2af08751546b1ab9
https://research.tue.nl/nl/publications/c52f5098-658f-4a71-8045-636415ce7154
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9
3-D CMOS Chip Stacking for Security ICs Featuring Backside Buried Metal Power Delivery Networks With Distributed Capacitance
Autor: Noriyuki Miura, Takaaki Okidono, Naoya Watanabe, Takuji Miki, Katsuya Kikuchi, Haruo Shimamoto, Makoto Nagata, Yuuki Araga, Hiroki Sonoda, Kazuki Monta
Publikováno v: IEEE Transactions on Electron Devices. 68:2077-2082
3-D stacks of complimentary metal–oxide–semiconductor (CMOS) integrated circuit (IC) chips for security applications monolithically embed backside buried metal (BBM) routing with low series impedance and high decoupling capability in a power deli
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::23c2541062860d3ec85e6769d7eda2e9
https://doi.org/10.1109/ted.2021.3058226
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10
Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices
Autor: Katsuya Kikuchi, Yuuki Araga, Noriyuki Miura, Takaaki Okidono, Makoto Nagata, Naoya Watanabe, Haruo Shimamoto, Takuji Miki, Hiroki Sonoda
Publikováno v: IEEE Journal of Solid-State Circuits. 55(10):2747-2755
This article presents a cryptographic key protection technique from physical security attacks through Si-backside of IC chip. Flip-chip packaging leads to a serious security hole that allows emerging backside physical security attacks. The proposed b
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9f8f312376f355db420e17e35dbcf789
https://hdl.handle.net/20.500.14094/0100476386
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