Zobrazeno 1 - 10
of 18
pro vyhledávání: '"Takeshi Okazawa"'
Autor:
T. Urai, K.-i. Oyama, T. Watanabe, T. Sato, K. Ninomiya, T. Jinbo, Takeshi Okazawa, M. Koike, H. Nakata, N. Kodama, K. Hashimoto
Publikováno v:
IEEE Journal of Solid-State Circuits. 27:1547-1554
A 5-V-only 16-Mb CMOS flash memory with sector erase mode is described. An optimized memory cell with diffusion self-aligned drain structure and channel erase are keys to achieving 5-V-only operation. By adopting this erase method and row decoders to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::20703dfacc2fa5403ff17047c2507055
https://doi.org/10.1109/4.165335
https://doi.org/10.1109/4.165335
Publikováno v:
International Technical Digest on Electron Devices Meeting.
A 2.0- mu m*1.8- mu m floating-gate-type memory cell, based on a 0.6- mu m design rule, has been developed for 16-Mb EPROMs (electrically programmable ROMs). The cell size is about 40% that of the smallest 4-Mb EPROM cell reported so far. The cell al
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::baf96813de1cf0ee8bac290de075ccae
https://doi.org/10.1109/iedm.1989.74348
https://doi.org/10.1109/iedm.1989.74348
Autor:
Kohji Kanamori, Akihiko Ishitani, Takeshi Okazawa, Y. Suzuki, M. Tsukiji, E. Hasegawa, Yosiaki S. Hisamune, Taishi Kubota
Publikováno v:
Proceedings of IEEE International Electron Devices Meeting.
A novel contactless cell with high capacitive-coupling ratio (HiCR) of 0.8, which is programmed and erased by Fowler-Nordheim tunneling, has been developed for 3 V-only 64 Mbit and future flash memories. A 1.50 /spl mu/m/sup 2/ cell area is obtained
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::161a333c7c0801f3040299b722a3502b
https://doi.org/10.1109/iedm.1993.347408
https://doi.org/10.1109/iedm.1993.347408
Autor:
Toshio Takeshima, Yosiaki S. Hisamune, I. Sasaki, T. Murotani, Kohji Kanamori, Takeshi Okazawa, Hiroshi Sugawara, Hiroshi Takada
Publikováno v:
Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.
A 3.3 V single-power-supply 64 Mb (4M words x 16b) flash memory with a dynamic bit-line latch (DBL) programming has 50 ns access time and 256 b erase/programming unit-capacity using hierarchical word- and bit-line structures and DBL programming. This
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::577b86d15b8cfa10b70394d7d610415d
https://doi.org/10.1109/isscc.1994.344693
https://doi.org/10.1109/isscc.1994.344693
Autor:
N. Nishio, N. Kodama, M. Matsuo, Mitsuhiro Horikawa, Shuichi Saito, Taishi Kubota, Takeshi Okazawa, Satoru Muramatsu, K. Arai, H. Shirai
Publikováno v:
Proceedings of 1994 IEEE International Electron Devices Meeting.
Clear evidence is presented that the floating gate poly-Si grain size dominates flash memory erase characteristics. Smaller grain size shows a narrower erase distribution. Thus conventional scaling theories should be modified to include that grain si
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b918d2127ac92becd224ec521ec72b97
https://doi.org/10.1109/iedm.1994.383280
https://doi.org/10.1109/iedm.1994.383280
Publikováno v:
International Electron Devices Meeting 1991 [Technical Digest].
A 0.4- mu m stacked gate cell for a 64-Mb flash memory has been developed which has the symmetrical side wall diffusion self-aligned (SSW-DSA) structure. Using the proposed SSW-DSA cell with p/sup +/ pockets at both the drain and the source, an adequ
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d7e24f00762dcd07e0d67efdb748a216
https://doi.org/10.1109/iedm.1991.235443
https://doi.org/10.1109/iedm.1991.235443
Publikováno v:
Proceedings of International Electron Devices Meeting.
A 0.54 /spl mu/m/sup 2/ self-aligned memory cell with hemispherical-grained (HSG) poly-Si floating gate (SAHF cell) has been developed for 256 Mbit flash memories. Applying hemispherical-grained (HSG) poly-Si to floating gate extends the upper surfac
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::36fb5af85109f37f06a56ca1cea1cedf
https://doi.org/10.1109/iedm.1995.499304
https://doi.org/10.1109/iedm.1995.499304
Publikováno v:
1991 Symposium on VLSI Technology.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c8da3a194ae2a74449ed6f185d7b01b1
https://doi.org/10.1109/vlsit.1991.705997
https://doi.org/10.1109/vlsit.1991.705997
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Akademický článek
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