Zobrazeno 1 - 10
of 24
pro vyhledávání: '"Takeshi Okagaki"'
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 19:97-103
This paper discusses the design methodology of a voltage and temperature-sensitive ring oscillator (VT_RO), whose frequency has a similar dependence on voltages and temperatures as that of worn-out stress strength of a gate time-dependent dielectric
Publikováno v:
IET Circuits, Devices & Systems. 12:182-188
The authors propose an on-chip wear-out monitoring technique, which is based on monitoring the environmental conditions experienced by a digital circuit. The frequency of the T-sensitive ring oscillator (RO) emulates the wear-out stress strength caus
Autor:
Hong-Hyun Park, Weiyi Qi, Jihye Shin, Takeshi Okagaki, Woosung Choi, Yong-Hee Park, Uihui Kwon, Saetbyeol Ahn, Young-seok Song, Yang Lu, Jing Wang, Minkyoung Kim, Sung-Yeol Kim, Nuo Xu, Ah-Young Kim, Dae Sin Kim, Jongchol Kim, Yohan Kim
Publikováno v:
2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).
Intelligent design technology co-optimization (iDTCO) methodology for next generation logic architecture pathfinding and its application results are presented in this paper. There are 2 major steps in our iDTCO framework; standard cell (STC)-level iD
Autor:
H. Ishida, Yasuo Inoue, Hiroyuki Takashino, M. Taya, K. Ishikawa, Motoaki Tanizawa, Takeshi Okagaki, T. Hayashi
Publikováno v:
IEEE Transactions on Electron Devices. 59:3199-3204
In this paper, we propose a comprehensive model to express nMOSFET threshold voltage shift induced by stress, ranging from a high tensile one to a high compressive one. Using this model, the quantum confinement effect, combined with large out-of-plan
Publikováno v:
ESSCIRC
We propose wear-out estimator of remaining lifetime, which consists of two types of custom ring oscillators (ROs) and cumulative stress counters only. This on-chip estimator operates independently without disruption of MCU main operations and is aime
Autor:
Shinji Tanaka, Takeshi Okagaki, Yasumasa Tsukamoto, Miki Tanaka, Masao Morimoto, Yuichiro Ishii, Yoshisato Yokoyama, Koji Tanaka, Makoto Yabuuchi, Koji Nii
Publikováno v:
2015 IEEE International Electron Devices Meeting (IEDM).
We examine appropriate bitcell layouts for two read/write (2RW) 8T dual-port (DP) SRAM in advanced planar/FinFET technologies. 256-kbit 2RW DP SRAM macros with highly symmetrical 8T DP bitcell were designed and fabricated using 16 nm FinFET technolog
Autor:
Takeshi Okagaki, O. Tsuchiya, Eiji Tsukuda, Hiroyuki Takashino, K. Ishikawa, Katsumi Eikyu, Y. Inoue, T. Hayashi, Shoji Wakahara, Motoaki Tanizawa, T. Uchida
Publikováno v:
IEEE Transactions on Electron Devices. 55:2632-2640
In this paper, we propose a new analytical electron mobility model in strained Si inversion layers suitable for implementation in a drift-diffusion simulator. Using our new model, a numerical study in conjunction with comprehensive bending experiment
Autor:
Y. Nishida, Yasuo Inoue, Takeshi Okagaki, J. Yugami, Hidekazu Oda, Tomohiro Yamashita, Y. Miyagawa, Kentaro Shibahara
Publikováno v:
Japanese Journal of Applied Physics. 47:2569-2574
New materials often force modification in a metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process and a device structure. In our investigation, a high-stress silicon nitride (SiN) contact etch stopper layer (CESL), which
Autor:
Yasumasa Tsukamoto, Kazunori Onozawa, Hiroaki Matsushita, Takeshi Okagaki, H. Ojiro, Masao Morimoto, Koji Shibutani, Koji Nii
Publikováno v:
Proceedings of the 2015 International Conference on Microelectronic Test Structures.
An area effective delay cell can be achieved in FinFET device with effective utilization of its parasitic capacitance, even though it is considered as disadvantage. We confirmed that parasitic capacitance of local interconnect can be a benefit for a