Zobrazeno 1 - 10
of 30
pro vyhledávání: '"Takayuki Shibasaki"'
Autor:
Manabu Ozawa, Eri Kawakami, Reiko Sakamoto, Takayuki Shibasaki, Akiteru Goto, Nobuaki Yoshida
Publikováno v:
Stem Cell Research, Vol 13, Iss 1, Pp 75-87 (2014)
Two distinct types of embryonic pluripotent stem cells can be established from either the inner cell mass (ICM) of preimplantation blastocyst (leukemia inhibitory factor (LIF)-dependent embryonic stem cell, ESC, called naive state) or the epiblast of
Externí odkaz:
https://doaj.org/article/cb7da2f0d13248c6a4b2d49a19390649
Autor:
Hirotaka Tamura, Ali Sheikholeslami, Mohammad Bagherbeik, Wahid Rahman, Danny Yoo, Takayuki Shibasaki
Publikováno v:
IEEE Solid-State Circuits Letters. 2:252-255
This letter presents the design details of a 36-Gb/s adaptive baud-rate clock and data recovery circuit (CDR) with continuous-time linear equalizers and 1-tap decision feedback equalizer (DFE) fabricated in 28-nm CMOS. The proposed on-chip adaptation
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2b75a059b9fd9eb077f4ab90a5e210e3
https://doi.org/10.1109/lssc.2019.2936768
https://doi.org/10.1109/lssc.2019.2936768
Publikováno v:
2021 IEEE 8th International Conference on Industrial Engineering and Applications (ICIEA).
To cope with daily changes in manufacturing production orders and plans, more efficient scheduling of production is highly required. The job-shop scheduling problem (JSP) provides a way to solve the production planning problem automatically, and the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6a30680938a8034dc6ecc2fa2cde4e80
https://doi.org/10.1109/iciea52957.2021.9436798
https://doi.org/10.1109/iciea52957.2021.9436798
Autor:
Kazuya Takemoto, Takayuki Shibasaki, Satoshi Matsubara, Toshiyuki Miyazawa, Yasuhiro Watanabe, Motomu Takatsu, Hirotaka Tamura
Publikováno v:
ASP-DAC
A Digital Annealer (DA) is a dedicated architecture for high-speed solving of combinatorial optimization problems mapped to an Ising model. With fully coupled bit connectivity and high coupling resolution as a major feature, it can be used to express
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::69aaee8fe0d9f0399b52318ef737b4c7
https://doi.org/10.1109/asp-dac47756.2020.9045100
https://doi.org/10.1109/asp-dac47756.2020.9045100
Autor:
Ali Sheikholeslami, Takayuki Shibasaki, Hirotaka Tamura, Joshua Liang, Hisakatsu Yamaguchi, Wahid Rahman, Danny Yoo
Publikováno v:
IEEE Journal of Solid-State Circuits. 52:3517-3531
This paper presents a referenceless baud-rate clock and data recovery (CDR) incorporated with a continuous-time linear equalizer (CTLE) and one-tap decision feedback equalizer (DFE) to achieve data rates from 22.5 to 32 Gb/s across a channel with Nyq
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0ef193dbea3447e026af6d62357a6de4
https://doi.org/10.1109/jssc.2017.2744661
https://doi.org/10.1109/jssc.2017.2744661
Autor:
Takayuki Shibasaki, Danny Yoo, Hirotaka Tamura, Mohammad Bagherbeik, Ali Sheikholeslami, Wahid Rahman
Publikováno v:
CICC
This paper presents a 2x half-baud-rate clock and data recovery technique that locks to the edge by performing 2x oversampling at half-baud-rate (every other UI). A test-chip was fabricated in TSMC 28nm HPC CMOS technology demonstrating a 30 Gb/s 2x
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2bddb761744c5bf57c81e60e67d7d936
https://doi.org/10.1109/cicc.2019.8780251
https://doi.org/10.1109/cicc.2019.8780251
Autor:
Ali Sheikholeslami, Danny Yoo, Takayuki Shibasaki, Wahid Rahman, Hirotaka Tamura, Mohammad Bagherbeik
Publikováno v:
ISSCC
Baud-rate clock-and-data recovery circuits (CDR) are ubiquitous in recent receiver designs as a means of lowering power consumption by sampling the data only once per UI. To further reduce power, prior works in pattern-based baud-rate PD [1] and FD [
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c33b0d93cfdcdb6aaebba99f3aad7452
https://doi.org/10.1109/isscc.2019.8662379
https://doi.org/10.1109/isscc.2019.8662379
Publikováno v:
ISSCC
Since the invention of optical fiber in the 1970's, optical communication has been changing the landscape of telecommunication and data communication worldwide with its ultra-broad bandwidth and long haul transmission capabilities. It connects people
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d945a136bd70247b83a5d6ce1b70a075
https://doi.org/10.1109/isscc.2018.8310407
https://doi.org/10.1109/isscc.2018.8310407
Autor:
Hisakatsu Yamaguchi, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki, Danny Yoo, Joshua Liang, Wahid Rahman
Publikováno v:
ISSCC
Baud-rate clock and data recovery circuits (CDRs) are becoming more prevalent in high-speed receiver designs as they offer lower power consumption by sampling the received data only once per UI [1,2]. This reduces the number of front-end comparators
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::41af4c4146da557a8e36c8588b16297e
https://doi.org/10.1109/isscc.2017.7870290
https://doi.org/10.1109/isscc.2017.7870290
Publikováno v:
ISSCC
The continuous growth of the internet and of big data infrastructure drives the ever-increasing demand for data communication bandwidth between chips. In this context, wireline transceiver data rate, energy efficiency, and area are extremely critical
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e13814382611cef5c72d4174e6a363c8
https://doi.org/10.1109/isscc.2017.7870284
https://doi.org/10.1109/isscc.2017.7870284