Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Takamasa Usui"'
Autor:
Toshiaki Hasegawa, Kiyotaka Tabuchi, Hideaki Masuda, K. Watanabe, Hideshi Miyajima, Hideki Shibata, Takamasa Usui
Publikováno v:
Japanese Journal of Applied Physics. 45:1570-1574
The effect of plasma treatment and a dielectric diffusion barrier on electromigration (EM) performance was examined. The characteristics and adhesion properties at the interface between copper (Cu) and the dielectric diffusion barrier were also inves
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::336497c5ee9b96ec29017522044b0766
https://doi.org/10.1143/jjap.45.1570
https://doi.org/10.1143/jjap.45.1570
Publikováno v:
Japanese Journal of Applied Physics. 43:6957-6962
The electromigration (EM) of Al-0.5 wt%Cu/Nb-based liner dual damascene (DD) interconnects is investigated for the first time. It is found that EM-induced voids nucleate in the line around the via at the cathode end of the line and their number decre
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::82803f730488f53ebe8fe1ea45ffa190
https://doi.org/10.1143/jjap.43.6957
https://doi.org/10.1143/jjap.43.6957
Autor:
Hosadurga Shobha, Yunpeng Yin, Terry A. Spooner, M. Tagami, M. Ishikawa, K. Shimada, E. Soda, S. H. Chen, John C. Arnold, Nicole Saulnier, Christopher J. Waskiewicz, Matthew E. Colburn, Takamasa Usui
Publikováno v:
2012 IEEE International Interconnect Technology Conference.
Three metal level 56nm-pitch Cu dual damascene interconnects in k2.7 low-k ILD have been demonstrated by using sidewall-image-transfer (SIT) patterning scheme to investigate the feasibility of the SIT process for sub 50nm-pitch technology node. 45nm-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a6c50ceece8771771e5c220115170966
https://doi.org/10.1109/iitc.2012.6251664
https://doi.org/10.1109/iitc.2012.6251664
Autor:
T. Levin, James J. Kelly, Shyng-Tsong Chen, Guillaume Landie, Stephan A. Cohen, John C. Arnold, Anthony Francis Scaduto, Takamasa Usui, Kazumichi Tsumura, M. Tagami, Hosadurga Shobha, Scott Halle, D. Horak, C-S. Koay, Sean D. Burns, Hideyuki Tomizawa, Muthumanickam Sankarapandian, Mignot Yann, M. Ishikawa, O. van der Straten, Yunpeng Yin, Donald F. Canaperi, Yongan Xu, Hirokazu Kato, Terry A. Spooner, Erin Mclellan, Matthew E. Colburn
Publikováno v:
2011 IEEE International Interconnect Technology Conference.
This work demonstrates the building of 64 nm pitch copper single and dual damascene interconnects using pitch split double patterning scheme to enable sub 80nm pitch patterning. A self-aligned-via (SAV) litho/RIE scheme was used to create vias confin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ef6cdcf3a50815fac6aedb7957a27fcf
https://doi.org/10.1109/iitc.2011.5940273
https://doi.org/10.1109/iitc.2011.5940273
Autor:
Hirokazu Kato, J. Maniscalco, Kazumichi Tsumura, D. Horak, John C. Arnold, Guillaume Landie, Shyng-Tsong Chen, Hideyuki Tomizawa, Hosadurga Shobha, O. van der Straten, Muthumanickam Sankarapandian, Sean D. Burns, Takamasa Usui, Terry A. Spooner, Yunpeng Yin, Tuan A. Vo, Chiew-seng Koay, Matt Colburn, M. Tagami, James J. Kelly, M. Ishikawa
Publikováno v:
2011 IEEE International Interconnect Technology Conference.
A self-aligned via(SAV) process was employed to build 64nm pitch Dual-Damascene(DD) interconnects using a pitch split double exposure pattering scheme to form the Cu lines. TiN hardmask (HM) density and thickness were optimized to achieve the SAV pro
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1b50f9842b6c66eec5a97dbf1369162c
https://doi.org/10.1109/iitc.2011.5940305
https://doi.org/10.1109/iitc.2011.5940305
Autor:
Leo Tai, Philip L. Flaitz, Samuel S. Choi, M. Zaitz, J. Schmatz, Stephan A. Cohen, H. Chen, Son Nguyen, Yun-Yu Wang, Terry A. Spooner, R. Murphy, John C. Arnold, P. Kozlowski, F. Chen, Eric G. Liniger, Oscar van der Straten, T. Bolom, Cyril Cabral, Kazumichi Tsumura, Tuan A. Vo, James J. Kelly, C.-K. Hu, Griselda Bonilla, S. H. Chen, Patrick W. DeHaven, S-H. Rhee, Christopher Parks, Christopher J. Penny, T. Lee, Baozhen Li, Donald F. Canaperi, J. Maniscalco, Clevenger Leigh Anne H, Frieder H. Baumann, T. Ryan, Takeshi Nogami, B. St. Lawrence, Steven E. Molis, F. Ito, Anita Madan, Cathryn Christiansen, Hosadurga Shobha, A. Simon, Takamasa Usui, R. J. Davis, Daniel C. Edelstein, B-Y. Kim
Publikováno v:
2010 International Electron Devices Meeting.
A 32 nm BEOL with PVD CuMn seedlayer and conventional PVD-TaN/Ta liner was fully characterized by fundamental, integrated, and reliability methods. CuMn was confirmed to have fundamental advantages over CuAl, such as higher electromigration (EM) reli
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::809a6e187b116c24e04d239c1b798618
https://doi.org/10.1109/iedm.2010.5703471
https://doi.org/10.1109/iedm.2010.5703471
Autor:
James Ren, James J. Kelly, M. Fujiwara, Takamasa Usui, Kazunari Ishimaru, Terry A. Spooner, Sunny Chiang, Tuan Vo, T. Watanabe, Mariko Takayanagi, Atsunobu Isobayashi, Charles W. Koburger, J. Maniscalco
Publikováno v:
2009 IEEE International Interconnect Technology Conference.
We have demonstrated the complete copper filling of contact structures at 32 nm- and 22 nm-node dimensions with the conventional PVD only Ta(N)/Cu barrier/seed process. Copper seed process was optimized to obtain the sufficient coverage of copper alo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::72f876202ad36a9abfe6c2156fb72fdb
https://doi.org/10.1109/iitc.2009.5090325
https://doi.org/10.1109/iitc.2009.5090325
Autor:
Akifumi Gawase, Hideyuki Tomizawa, Takamasa Usui, Tadayoshi Watanabe, Yumi Hayashi, Kei Watanabe, Hideki Shibata, Miyoko Shimada
Publikováno v:
2008 International Interconnect Technology Conference.
Porous Low-k dielectric (k=2.0) was applied for Copper (Cu) dual-damascene interconnect with SiOC/PAr hybrid dielectric. More than 90% yield for via was obtained and approximately 5% capacitance reduction in inter-layer was obtained compared with the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::63451338c9b3a1ef714dbeaeb3ab1692
https://doi.org/10.1109/iitc.2008.4546969
https://doi.org/10.1109/iitc.2008.4546969
Autor:
Tadayoshi Watanabe, Junichi Wada, H. Matsuyama, H. Matsumori, Masahiko Hasunuma, K. Nomura, Takamasa Usui, M. Kitamura
Publikováno v:
2008 International Interconnect Technology Conference.
We have developed highly reliable low resistance copper contact technology for CMOS device beyond 32nm node. Cu contact is expected to reduce contact resistance but degradation of device performance caused by Cu diffusion into Si and filling failure
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7dfab6768e3eecd12f4a39d41c8be691
https://doi.org/10.1109/iitc.2008.4546924
https://doi.org/10.1109/iitc.2008.4546924
Autor:
Gaku Minamihaba, Yoshihiro Uozumi, Kazumichi Tsumura, Takamasa Usui, H. Sawada, H. Toyoda, Hideshi Miyajima, Akihiro Kojima, Yumi Hayashi, Kei Watanabe, Miyoko Shimada, Hayato Nasu, Hideki Shibata, S. Ito
Publikováno v:
2006 International Interconnect Technology Conference.
In order to realize the effective dielectric constant (k eff)=2.4 for 32 nm-node copper (Cu) dual-damascene (DD) interconnects, a spin-on-dielectric (SOD) SiOC (k=2.0) as the inter-level dielectric and plasma-induced damage restoration treatment were
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2cf59a20a5b0977046b3a706a7f4c1e6
https://doi.org/10.1109/iitc.2006.1648692
https://doi.org/10.1109/iitc.2006.1648692