Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Takahisa Hiraide"'
Autor:
Kazuhiko Iwasaki, Masayuki Arai, Takahisa Hiraide, Satoshi Fukumoto, Hideaki Konishi, Tatsuru Matsuo, Michiaki Emori, Takashi Aikyo
Publikováno v:
IEICE Transactions on Information and Systems. :726-735
We developed test data compression scheme for scan-based BIST, aiming to compress test stimuli and responses by more than 100 times. As scan-BIST architecture, we adopt BIST-Aided Scan Test (BAST), and combines four techniques: the invert-and-shift o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ab4d7c4a3b29c9a4478996010e63add5
https://doi.org/10.1093/ietisy/e91-d.3.726
https://doi.org/10.1093/ietisy/e91-d.3.726
Publikováno v:
Electronics and Communications in Japan (Part II: Electronics). 90:58-65
It is common to use ATPG of scan-based design for high fault coverage in LSI testing. However, significant increases in test cost arise with increasing design complexity. Recent strategies for test cost reduction combine ATPG and BIST techniques. Unf
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::02bd9c0d9daebd8c0ff810f219ce7e3f
https://doi.org/10.1002/ecjb.20356
https://doi.org/10.1002/ecjb.20356
Autor:
Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Tatsuru Matsuo, Takahisa Hiraide, Hideaki Konishi, Michiaki Emori, Takashi Aikyo
Publikováno v:
ITC
The authors have developed a scheme for scan-based BIST that can compress test stimuli and responses by more than 100 times. The scheme is based on a scan-BIST architecture, and combines four techniques: the invert-and-shift operation, run-length com
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::83f73e17d2b1ad6b7d9d99da2f390044
https://doi.org/10.1109/test.2006.297664
https://doi.org/10.1109/test.2006.297664
Autor:
Takahisa Hiraide, Akira Kanuma, Tsuyoshi Mochizuki, Masahiro Yanagida, Shigeru Nagasawa, Chihiro Endoh, Yutaka Isoda, Yaroku Sugiyama, Takeshi Kono, Osamu Sugawara, Hitoshi Yamanaka, Kazunobu Adachi, Noriyuki Ito, Eizo Ninoi, Daisuke Maruyama
Publikováno v:
ASP-DAC
This paper present a case-study of delay defect screening applied to Fujitsu 2.16GHz SPARC64 microprocessor. A nonrobust delay test is used while each test vector is compacted to detect multiple transition faults in a standard scan-based design targe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2032801798ea402f995538c56aaac125
https://doi.org/10.1145/1118299.1118387
https://doi.org/10.1145/1118299.1118387
Autor:
Takahisa Hiraide, Kwame Osei Boateng, K. Itaya, Hideaki Konishi, T. Mochiyama, M. Emori, H. Yamanaka
Publikováno v:
VTS
It is common to use ATPG of scan-based design for high fault coverage in LSI testing. However, significant increase in test cost is caused in accordance with increasing design complexity. Recent strategies for test cost reduction combine ATPG and BIS
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3434030ba1d459152a54baab418d9266
https://doi.org/10.1109/vtest.2003.1197675
https://doi.org/10.1109/vtest.2003.1197675
Publikováno v:
2006 15th Asian Test Symposium; 2006, p131-131, 1p