Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Takaharu Itani"'
Publikováno v:
Japanese Journal of Applied Physics. 42:L1126-L1129
The advantages of using the new flash lamp annealing (FLA) technology and a shallow junction with the consequent low sheet resistivity for metal oxide silicon field effect transistors (MOSFETs) with gate length (L) of 20 nm were clarified by computer
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4b75d28753651e67099250dc1856d6d8
https://doi.org/10.1143/jjap.42.l1126
https://doi.org/10.1143/jjap.42.l1126
Autor:
Yoshiaki Toyoshima, Akira Hokazono, Toshitaka Miyata, Takaharu Itani, Satoshi Inaba, K. Adachi, Toshihiko Iinuma, Y. Oshima, H. Tsujii, Shigeru Kawanaka, Kiyotaka Miyano
Publikováno v:
2009 International Semiconductor Device Research Symposium.
The significance of impurity profile design for Source/Drain Extension (SDE) is widely recognized for deeply scaled MOSFET. In this paper, novel SDE formation scheme in planar pMOSFET is discussed using Plasma Doping (PD) and Laser Spike Annealing (L
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1912c752660ebb4309094af597888d5a
https://doi.org/10.1109/isdrs.2009.5378311
https://doi.org/10.1109/isdrs.2009.5378311
Autor:
T. Sanuki, Fumiyoshi Matsuoka, M. Oulmane, Takaharu Itani, Hisao Yoshimura, T. Sawada, Hisanori Aikawa, M. Ikeda, N. Kariya, Y. Akiyama, M. Iwai, Takahiro Ito, Osamu Fujii, R. Gull, N. Zographos
Publikováno v:
Extended Abstracts of the 2008 International Conference on Solid State Devices and Materials.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7bfc15597ff7338495a8e98b72ad9ea3
https://doi.org/10.7567/ssdm.2008.b-8-4
https://doi.org/10.7567/ssdm.2008.b-8-4
Publikováno v:
2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors.
In the optical annealing process, temperature distributions of chips on a silicon wafer tend to be inhomogeneous. One of sources to generate the temperature inhomogeneities should be an optical interference effect of the incident lights where the inc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7ce278b38e769a21343ed8d8b7192648
https://doi.org/10.1109/rtp.2008.4690542
https://doi.org/10.1109/rtp.2008.4690542
Autor:
Takaharu Itani, A. Eiho, K. Nagaoka, T. Komoda, Toshiyuki Iwamoto, K. Suguro, S. Mori, M. Nakazawa, Takahiro Ito, H. Yamazaki, Masaki Saito, Hisao Yoshimura, Kenichi Yoshino, Kiyotaka Imai, T. Shinyama, K. Nakayama, K. Miyagi, M. Iwai, M. Ikeda, A. Minej, Y. Enomoto, Keiichi Nakazawa, Hiroshi Naruse, T. Sanuki, Naoki Nagashima, T. Kuwata, S. Iwasa, K. Ota, K. Matsuo, Tsutomu Sato, Mitsuhiro Togo, Fumiyoshi Matsuoka, T. Kitano, Satoru Muramatsu, O. Fuji, K. Ohno, Keiichiro Yoshida, Ichiro Mizushima
Publikováno v:
2007 IEEE International Electron Devices Meeting.
This paper describes the fabrication and performance of CMOS transistors featuring flash lamp annealing (FLA) for 45 nm node. We show, for the first time, applying FLA prior to spike RTA as S/D annealing is effective to enhance the channel stress in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::afb922a32e402f0b2993df6155245a4e
https://doi.org/10.1109/iedm.2007.4418923
https://doi.org/10.1109/iedm.2007.4418923
Publikováno v:
2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).
Flash lamp annealing (FLA) was first applied to complementary MOSFETs (CMOS) as a new method of activating implanted impurities in source and drain. By optimizing ion implantation and activation annealing conditions, junction depth less than 10 nm wi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1a445d2447c0f51e2c54922df55ca0d9
https://doi.org/10.1109/vlsit.2003.1221082
https://doi.org/10.1109/vlsit.2003.1221082
Autor:
Takaharu Itani, H. Oguma, Yoshiaki Toyoshima, Toshihiko Iinuma, Hidemi Ishiuchi, H. Fukui, Atsushi Murakoshi, Akira Hokazono, M. Fujiwara, Satoshi Inaba, T. Kudo, T. Shimizu, S. Matsuda, Y. Watanabe, Mariko Takayanagi, Atsushi Azuma, S. Mori, Shunko Magoshi, K. Suguro, K. Adachi, S. Taniguchi, Yasuhiro Katsumata, T. Matsushita, Hideki Shibata, K. Okano, H. Oyamatsu, H. Suto, Kazuya Ohuchi
Publikováno v:
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).
The 35 nm gate length CMOS devices with oxynitride gate dielectric and Ni salicide have been fabricated to study the feasibility of higher performance operation. Nitrogen concentration in gate oxynitride was optimized to reduce gate current I/sub g/
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d8a0590867ef771806f1709e0c6c1c0f
https://doi.org/10.1109/iedm.2001.979590
https://doi.org/10.1109/iedm.2001.979590