Výsledky vyhledávání

Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization

Autor: Yoichi Momiyama, TaiYu Cheng, Jun Nagayama, Jun Chen, Yutaka Masuda, Masanori Hashimoto

Publikováno v: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. (3):497-508

Reducing power consumption is a crucial factor making industrial designs, such as mobile SoCs, competitive. Voltage scaling (VS) is the classical yet most effective technique that contributes to quadratic power reduction. A recent design technique ca

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a2b65867f68f27173fd6ad652cd5cde9
https://nagoya.repo.nii.ac.jp/records/2002730

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Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling

Autor: Tohru Ishihara, TaiYu Cheng, Jun Nagayama, Masanori Hashimoto, Yoichi Momiyama, Yutaka Masuda

Publikováno v: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. (3):509-517

This work proposes a design methodology that saves the power dissipation under voltage over-scaling (VOS) operation. The key idea of the proposed design methodology is to combine critical path isolation (CPI) and bit-width scaling (BWS) under the con

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e2ba7264100f29494bbc3a7ff25b7dc7
https://nagoya.repo.nii.ac.jp/records/2002731

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Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design

Autor: TaiYu Cheng, Jun Nagayama, Yutaka Masuda, Yoichi Momiyama, Masanori Hashimoto, Tohru Ishihara

Publikováno v: DATE

This work proposes a design methodology that saves the power under voltage over-scaling (VOS) operation. The key idea of the proposed design methodology is to combine critical path isolation (CPI) and bit-width scaling (BWS) under the constraint of c

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6e10963299512f918ce55e2544c717a5
https://nagoya.repo.nii.ac.jp/records/2002735

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GIS discharge induced by vibration, metal particles and VFTO

Autor: Bobo Zhan, Dong Wang, Xingquan Huang, Wenhan Wu, Taiyu Cheng, Ce Xu, Guoming Ma, Wei Wang, Xin Weifeng

Publikováno v: 2021 IEEE Electrical Insulation Conference (EIC).

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::9322a15e99c4458d4689f581ba8eb5c1
https://doi.org/10.1109/eic49891.2021.9612396

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Minimizing Energy of DNN Training with Adaptive Bit-Width and Voltage Scaling

Autor: Masanori Hashimoto, TaiYu Cheng

Publikováno v: ISCAS

Training DNN mostly relies on GPUs with FP32 format. While FP16 is acknowledged for its advantage of high computation and memory efficiencies for training DNN, the training must be accompanied with techniques dedicated for a particular dataset. There

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::11cee050e8fc094dfc9e1b55bef19a1e
https://doi.org/10.1109/iscas51556.2021.9401556

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Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization

Autor: Yoichi Momiyama, Yukata Masuda, Masanori Hashimoto, TaiYu Cheng, Jun Nagayama, Jun Chen

Publikováno v: ASP-DAC

This paper proposes a design optimization methodology that can achieve a mode-wise voltage scalable (MWVS) design with applying the activation-aware slack assignment (ASA). Originally, ASA allocates the timing margin of critical paths with a stochast

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a5209bbe24e58f5cd2a7c58ed0886215
https://doi.org/10.1145/3394885.3431575

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Logarithm-approximate floating-point multiplier is applicable to power-efficient neural network training

Autor: Jaehoon Yu, Yukata Masuda, TaiYu Cheng, Jun Chen, Masanori Hashimoto

Recently, emerging “edge computing” moves data and services from the cloud to nearby edge servers to achieve short latency and wide bandwidth, and solve privacy concerns. However, edge servers, often embedded with GPU processors, highly demand a

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1282c91905518b3eb330f6403fc81901
http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100827089

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Minimizing Power for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier

Autor: TaiYu Cheng, Jaehoon Yu, Masanori Hashimoto

Publikováno v: PATMOS

This paper proposes to adopt logarithm-approximate multiplier (LAM) for multiply-accumulate (MAC) computation in neural network (NN) training engine, where LAM approximates a floating-point multiplication as an addition resulting in smaller delay, fe

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::0f93382796ce28bdfabb3e0356dcf032
https://doi.org/10.1109/patmos.2019.8862162

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