Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Tai-Hsing Wen"'
Autor:
Ta-Wei Liu, Meng-Fan Chang, Yu-Der Chih, Je-Syu Liu, Chin-Yi Su, Ting-Wei Chang, Shih-Ying Wei, Tsung-Yuan Huang, Cheng-Xin Xue, Wei-Chen Wei, Je-Min Hung, Chun-Ying Lee, Tai-Hsing Wen, Mon-Shu Ho, Yi-Ren Chen, Yen-Kai Chen, Kea-Tiong Tang, Yun-Chen Lo, Jing-Hong Wang, Sheng-Po Huang, Chou Chung-Cheng, Shih-Hsih Teng, Chung-Chuan Lo, Chih-Cheng Hsieh, Ren-Shuo Liu, Hui-Yao Kao, Yen-Cheng Chiu, Tzu-Hsiang Hsu
Publikováno v:
Nature Electronics. 4:81-90
The development of small, energy-efficient artificial intelligence edge devices is limited in conventional computing architectures by the need to transfer data between the processor and memory. Non-volatile compute-in-memory (nvCIM) architectures hav
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3aab41f92e0ac34bcb2ba8315a23432a
https://doi.org/10.1038/s41928-020-00505-5
https://doi.org/10.1038/s41928-020-00505-5
Autor:
Jing-Hong Wang, Meng-Fan Chang, Yen-Kai Chen, Ta-Wei Liu, Cheng-Xin Xue, Tsung-Yuan Huang, Yi-Ren Chen, Hui-Yao Kao, Sheng-Po Huang, Yun-Chen Lo, Tzu-Hsiang Hsu, Chih-Cheng Hsieh, Chung-Chuan Lo, Je-Syu Liu, Tai-Hsing Wen, Wei-Chen Wei, Ren-Shuo Liu, Ting-Wei Chang, Shih-Ying Wei, Kea-Tiong Tang
Publikováno v:
ISSCC
Nonvolatile computing-in-memory (nvCIM) can improve the latency (t AC ) and energy-efficiency (EF MAC ) of tiny AI edge devices performing multiply-and-accumulate (MAC) computing after system wake-up. Prior nvCIMs have proven effective for binary inp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d1b24c69f896f2f7ef3e3ff16edff7ee
https://doi.org/10.1109/isscc19947.2020.9063078
https://doi.org/10.1109/isscc19947.2020.9063078
Autor:
Yun-Chen Lo, Yen-Chi Chou, Meng-Fan Chang, Qiang Li, Kea-Tiong Tang, Ruhui Liu, Wei-Chen Wei, Tzu-Hsiang Hsu, Yen-Kai Chen, Ssu-Yen Wu, Zhixiao Zhang, Xin Si, Wei-Chiang Shih, Yajuan He, Chung-Chuan Lo, Syuan-Hao Sie, Jing-Hong Wang, Chih-Cheng Hsieh, Ta-Wei Liu, Yung-Ning Tu, William Shih, Ren-Shuo Liu, Nan-Chun Lien, Jian-Wei Su, Wei-Hsing Huanq, Pei-Jung Lu, Tai-Hsing Wen
Publikováno v:
ISSCC
Advanced AI edge chips require multibit input (IN), weight (W), and output (OUT) for CNN multiply-and-accumulate (MAC) operations to achieve an inference accuracy that is sufficient for practical applications. Computing-in-memory (CIM) is an attracti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9d8713cef5e9bb39e2be552446bbe9a4
https://doi.org/10.1109/isscc19947.2020.9062995
https://doi.org/10.1109/isscc19947.2020.9062995
Autor:
Qian Chen, Fu-Chun Chang, Chih-Cheng Hsieh, Hyunjoon Kim, Wei-Chen Wei, Chung-Chuan Lo, Meng-Fan Chang, Yen-Kai Chen, Ren-Shuo Liu, Kea-Tiong Tang, Bongjin Kim, Tai-Hsing Wen, Yi-Ren Chen, Tzu-Hsiang Hsu
Publikováno v:
A-SSCC
This paper presents a 0.5V computational CMOS image sensor (C2IS) with array-parallel computing capability for always-on feature extraction. By applying the developed pulsed-width modulation (PWM) pixel and switch-current integration (SCI), the in-se
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::97505bba37c773e12bc4e43720688a20
https://doi.org/10.1109/a-sscc47793.2019.9056945
https://doi.org/10.1109/a-sscc47793.2019.9056945
Autor:
Wen-Chien Ting, Tai-Hsing Wen, Jun-Shen Wu, Yun-Chen Lo, Ren-Shuo Liu, Jian-Hao Huang, Yun-Sheng Chang, Yu-Chun Kuo
Publikováno v:
ESSCIRC
In this paper, a physically tightly coupled, logically loosely coupled, near-memory binary neural network accelerator (PTLL-BNN) is designed and fabricated. Both architecture-level and circuit-level optimizations are presented. From the perspective o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::90128cd08e9540b66706c36768bbb349
https://doi.org/10.1109/esscirc.2019.8902909
https://doi.org/10.1109/esscirc.2019.8902909
Autor:
Tzu-Hsiang Hsu, Zuo-Wei Yeh, Wei-Chen Wei, Meng-Fan Chang, Chung-Chuan Lo, Chih-Cheng Hsieh, Yu-Chun Kuo, Kea-Tiong Tang, Yen-Cheng Chiu, Ren-Shuo Liu, Cheng-Xin Xue, Tai-Hsing Wen, Mon-Shu Ho
Publikováno v:
VLSI Circuits
In quest to execute emerging deep learning algorithms at edge devices, developing low-power and low-latency deep learning accelerators (DLAs) have become top priority. To achieve this goal, data processing techniques in sensor and memory utilizing th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::23003607b0588f0f53a322348c8499d8
https://doi.org/10.23919/vlsit.2019.8776560
https://doi.org/10.23919/vlsit.2019.8776560