Zobrazeno 1 - 10
of 23
pro vyhledávání: '"Tadaaki Bandoh"'
Autor:
Tetsuo Nakano, Fumio Murabayashi, Tatsumi Yamauchi, Takashi Hotta, Hirozi Yamada, Y. Kobayashi, Tadaaki Bandoh, S. Tanaka
Publikováno v:
IEEE Journal of Solid-State Circuits. 29:298-302
This paper describes 3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor. The processor is implemented in a 0.5-/spl mu/m BiCMOS technology with 4-metal-layer structure. The chip includes a 240 MFLOPS fully pipelined 64-b floating point
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::54b6e20f63505caf492f74bb82a791aa
https://doi.org/10.1109/4.278351
https://doi.org/10.1109/4.278351
Autor:
Masahiro Iwamura, Shigemi Adachi, Shigeya Tanaka, Tadaaki Bandoh, Takashi Hotta, Seiji Iwamoto, Tatsumi Yamauchi, Atsuo Hotta
Publikováno v:
Electronics and Communications in Japan (Part II: Electronics). 74:44-52
A 70-MHz, 32-bit BiCMOS processor has been developed. This paper describes the architecture and the high-speed technology, mainly the arithmetic unit, of the very-high-speed BiCMOS processor. This processor includes a 32-bit ALU, register file with f
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::046cb9b6f4faa6406a25ee07ce967869
https://doi.org/10.1002/ecjb.4420740605
https://doi.org/10.1002/ecjb.4420740605
Publikováno v:
IEEE Journal of Solid-State Circuits. 25:770-777
A 70-MHz, 32-b microprocessor fabricated using BiCMOS macrocells is described. The chip contains about 529 k transistors, 521 k MOS transistors (98.5%), and 8 k bipolar transistors (1.5%). This small number of bipolar transistors increases the speed
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4240396919f120fb04edc2dc909bc6ec
https://doi.org/10.1109/4.102675
https://doi.org/10.1109/4.102675
Publikováno v:
The 16th Annual International Symposium on Computer Architecture.
This paper discusses an optimal memory system to realize a high performance integrated Prolog processor, the IPP. First, the memory access characteristics of Prolog are analyzed by a simulator, which simulates the execution of a Prolog program at a m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::65f5401b860fc24473d0ff868ba6802b
https://doi.org/10.1109/isca.1989.714555
https://doi.org/10.1109/isca.1989.714555
Publikováno v:
ICCD
System requirements for VLSI technologies are reviewed and circuit technologies for BiCMOS VLSIs as computer elements are described. The following topics are dealt with: circuits for logic gates-conventional circuits and feedback type circuits for fi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6960bf6a24605494bfe16d11c8834c41
https://doi.org/10.1109/iccd.1989.63380
https://doi.org/10.1109/iccd.1989.63380
Autor:
Yasuhiro Nakatsuka, Takashi Hotta, S. Nakagami, T. Nakano, Shigemi Adachi, Atsuo Hotta, S. Tanaka, Tadaaki Bandoh, R. Satomura, T. Moriyama, S. Iwamoto
Publikováno v:
ICCD
The authors have developed the world's first BiCMOS 32-b single-chip microprocessor. It integrates 529 K transistors into a 12.98-mm/sup 2/ chip and typically realizes a 70-MHz frequency. The frequency is 1.5-2 times higher than that of current CMOS
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b1aa3233aa3f8faf9b988af095b91775
https://doi.org/10.1109/iccd.1989.63387
https://doi.org/10.1109/iccd.1989.63387
Publikováno v:
Scopus-Elsevier
The IPP was developed to realize high-speed execution of Prolog and procedural languages on the same computer with less overhead. Previously developed optimization techniques such as clause indexing by optimal argument and global register assignment
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::262de7ac5c136db868b34b332d471f61
https://doi.org/10.1109/aiia.1988.13339
https://doi.org/10.1109/aiia.1988.13339
Publikováno v:
ICCD
A means of describing computer models on a high level and a means of generating the necessary data about the model for simulation are presented. The method is exemplified by using it to describe a RISC processor model. The debugging environment and i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8e95672dde726e8388e25867599ef6b6
https://doi.org/10.1109/iccd.1992.276261
https://doi.org/10.1109/iccd.1992.276261
Publikováno v:
ACM Multimedia
High performance and high quality for continuous media stream delivery needed by streaming server systems cannot be achieved efficiently using general-purpose operating systems, due to the overhead of the I/O mechanism implementation generally used.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e53e54e5ab65627863aa68996fe6452a
https://doi.org/10.1145/641007.641088
https://doi.org/10.1145/641007.641088
Autor:
Yasuhiro Nakatsuka, Takashi Hotta, Shigeya Tanaka, Tadaaki Bandoh, Ryuichi Satomura, Syuichi Nakagami, Tetsuo Nakano, Atsuo Hotta, Takashi Moriyama, Shigemi Adachi, Shoji Iwamoto
Publikováno v:
High-Performance System Design; 1999, p108-111, 4p