Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Tad Grider"'
Autor:
Tad Grider, Steve Heinrich-Barna, John Howard Macpeak, Armando Vigil, Brian Horning, Kelly DeShields, Brian K. Kirkpatrick, Alexander Kotov, C.F. Dunn, N. Do, Kim Jinho, Lyndon Preiss, Jon Nafziger, O'brien Corey Rollin, Viktor Markov, Sean Bo
Publikováno v:
IRPS
In advanced embedded split-gate SuperFlash® 3rd generation technology (ESF3) the select gate is compiled with continually scaled core logic transistors. In doing so, enhanced performance and lower power are achieved. However, it was observed during
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::821ca4dab5ce07eada43d00484b00de1
https://doi.org/10.1109/irps45951.2020.9128829
https://doi.org/10.1109/irps45951.2020.9128829
Publikováno v:
Microelectronics Reliability. 39:673-679
There are several advanced processes which are being actively studied as candidates for sub-0.25 μm technology. This paper studies the effects on NMOS hot carrier reliability from remote plasma nitrided oxide (RPNO), deuterium anneal and pocket impl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a1470425faee103b0a9c98a8097f8318
https://doi.org/10.1016/s0026-2714(99)00033-5
https://doi.org/10.1016/s0026-2714(99)00033-5
Autor:
Shaofeng Yu, Brian K. Kirkpatrick, O'brien Corey Rollin, Larry Liu, Rajesh Khamankar, Oluwamuyiwa Oluwagbemiga Olubuyide, Deborah J. Riley, Anand T. Krishnan, I. Fujii, C. Machala, Clinton L. Montgomery, Brian Hornung, H. Bu, Yiming Gu, Steven L. Prins, T. Lowry, K. Kirmse, James Walter Blatchford, Tad Grider, C. Bowen, G. Shinn, D. Corum, C. Lin, Tony Tae-Hyoung Kim
Publikováno v:
2008 Symposium on VLSI Technology.
A 45 nm high performance technology with 11 level metallization is presented for SOC applications. High performance and density are maintained through new process optimizations that allow the use of less restrictive layouts by eliminating defect gene
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e24ec331746ae0843044248c5da8aaa5
https://doi.org/10.1109/vlsit.2008.4588608
https://doi.org/10.1109/vlsit.2008.4588608
Autor:
Tad Grider, Clinton L. Montgomery, D. Mercer, Freidoon Mehrad, Donald S. Miles, Shaofeng Yu, Richard L. Guldi, B.Y. Lin, Yuqing Xu, Yaw S. Obeng, Sue E. Crank, D. Corum, A. J. Griffin, P J. Chen, F.S. Johnson, D.A. Ramappa, X. Liu, Jiong-Ping Lu, Thomas D. Bonifield, Juanita Deloach, Duofeng Yue, Lance S. Robertson, Lindsey H. Hall
Publikováno v:
2006 International Workshop on Junction Technology.
As CMOS technologies move into the 90nm node and beyond, nickel (Ni) self-aligned silicide (SALICIDE) is transitioning from R&D into mainstream SC fabrication. In this paper, advantages and challenges of Ni SALICIDE process technology will be reviewe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::59465f5a5541a0701c33e53de7ce1352
https://doi.org/10.1109/iwjt.2006.220877
https://doi.org/10.1109/iwjt.2006.220877
Autor:
Rajesh Khamankar, Joe G. Tran, P.E. Nicollian, Anand T. Krishnan, Melissa M. Hewson, S. Aur, Mark Somervell, James Walter Blatchford, Tad Grider, Lindsey H. Hall, Brian K. Kirkpatrick, D. Farber, Srinivasan Chakravarthi, Benjamen Michael Rathsack, H. Bu, Brian Hornung, Juanita Deloach, Brian A. Smith, Jiong-Ping Lu, C. Kaneshige, April Gurba, C. Bowen, C. Machala, Donald S. Miles, Husam N. Alshareef, M. J. Bevan, P.R. Chidambaram, Vladimir A. Ukraintsev, Ajith Varghese, Hiroaki Niimi
Publikováno v:
Scopus-Elsevier
In this abstract we present a highly manufacturable, high performance 90nm technology with best in class performance for 35nm gate-length N and P transistors. Unique, but simple and low cost, process changes have been utilized to modulate channel str
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7bea0f7129ea088a7c5308d5ef089297
https://doi.org/10.1109/vlsit.2004.1345456
https://doi.org/10.1109/vlsit.2004.1345456
Autor:
D. Mercer, Melissa M. Hewson, Tad Grider, Clinton L. Montgomery, R. Kuan, L. Tsung, Donald S. Miles, J. Ruan, J. Zhao, April Gurba, C.T. Lin, Jiong-Ping Lu, Y. Xu
Publikováno v:
Digest. International Electron Devices Meeting.
A novel nickel self-aligned silicide (SALICIDE) process technology has been developed for CMOS devices with physical gate length of sub-40 nm. The excess silicidation problem due to edge effect is effectively solved by using a low-temperature, in-sit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6eae55f6a0c71ccde57a5b0c8a7d2356
https://doi.org/10.1109/iedm.2002.1175855
https://doi.org/10.1109/iedm.2002.1175855
Autor:
Rajesh Khamankar, Lancy Tsung, Mark R. Visokay, M. Douglas, A. Shanware, Luigi Colombo, M. J. Bevan, R. T. Laaksonen, R. Kuan, Tad Grider, Haowen Bu, J. McPherson, James J. Chambers, Antonio L. P. Rotondaro
Publikováno v:
2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).
We report for the first time on short channel transistors fabricated using HfSiON, a new high-k gate dielectric material. HfSiON has superior electrical characteristics such as low leakage current relative to SiO/sub 2/, low interfacial trap density,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2e5c8ec14031857e428673f9341b6f3a
https://doi.org/10.1109/vlsit.2002.1015428
https://doi.org/10.1109/vlsit.2002.1015428
Autor:
Husam N. Alshareef, Juanita Deloach, M. J. Bevan, C. Bowen, M. Goodwin, P.R. Chidambaram, James Walter Blatchford, Srinivasan Chakravarthi, Tad Grider, Brian K. Kirkpatrick, Rajesh Khamankar, April Gurba, Ajith Varghese, Hiroaki Niimi, Donald S. Miles, Brian A. Smith, Xin Zhang, C. Machala, Jiong-Ping Lu, Lance S. Robertson, G.V. Thakar, Benjamen Michael Rathsack, Brian Hornung, P.E. Nicollian
Publikováno v:
2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).
A 90 nm logic technology is presented featuring an aggressively scaled 37 nm gate length, 1.3 nm EOT plasma nitrided gate dielectric with differential offset spacer and leading edge CV/I performance. NMOS and PMOS transistors have been optimized with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4f9fff4d3ed93400052c81221e1ec69b
https://doi.org/10.1109/vlsit.2003.1221098
https://doi.org/10.1109/vlsit.2003.1221098
Publikováno v:
1998 IEEE International Reliability Physics Symposium Proceedings 36th Annual (Cat No 98CH36173) RELPHY-98.
There are several advanced processes which are being actively studied as candidates for sub-0.25 /spl mu/m technology and beyond. This paper studies the effects on hot carrier reliability from remote plasma nitrided oxide (RPNO), deuterium anneal and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::86093ffa6bf9cddf6ecfba81da3599a9
https://doi.org/10.1109/relphy.1998.670512
https://doi.org/10.1109/relphy.1998.670512
Conference
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