Zobrazeno 1 - 10
of 38
pro vyhledávání: '"TOSORATTO, LAURA"'
Autor:
Paolucci, Pier Stanislao, Bacivarov, Iuliana, Rai, Devendra, Schor, Lars, Thiele, Lothar, Yang, Hoeseok, Pastorelli, Elena, Ammendola, Roberto, Biagioni, Andrea, Frezza, Ottorino, Cicero, Francesca Lo, Lonardo, Alessandro, Simula, Francesco, Tosoratto, Laura, Vicini, Piero
The EURETILE project required the selection and coding of a set of dedicated benchmarks. The project is about the software and hardware architecture of future many-tile distributed fault-tolerant systems. We focus on dynamic workloads characterised b
Externí odkaz:
http://arxiv.org/abs/1408.4587
Autor:
Ammendola, Roberto, Biagioni, Andrea, Frezza, Ottorino, Cicero, Francesca Lo, Paolucci, Pier Stanislao, Lonardo, Alessandro, Rossetti, Davide, Simula, Francesco, Tosoratto, Laura, Vicini, Piero
Modern Graphics Processing Units (GPUs) are now considered accelerators for general purpose computation. A tight interaction between the GPU and the interconnection network is the strategy to express the full potential on capability computing of a mu
Externí odkaz:
http://arxiv.org/abs/1311.1741
Autor:
Ammendola, Roberto, Biagioni, Andrea, Fantechi, Riccardo, Frezza, Ottorino, Lamanna, Gianluca, Cicero, Francesca Lo, Lonardo, Alessandro, Paolucci, Pier Stanislao, Pantaleo, Felice, Piandani, Roberto, Pontisso, Luca, Rossetti, Davide, Simula, Francesco, Sozzi, Marco, Tosoratto, Laura, Vicini, Piero
We implemented the NaNet FPGA-based PCI2 Gen2 GbE/APElink NIC, featuring GPUDirect RDMA capabilities and UDP protocol management offloading. NaNet is able to receive a UDP input data stream from its GbE interface and redirect it, without any intermed
Externí odkaz:
http://arxiv.org/abs/1311.1010
Autor:
Paolucci, Pier Stanislao, Ammendola, Roberto, Biagioni, Andrea, Frezza, Ottorino, Cicero, Francesca Lo, Lonardo, Alessandro, Pastorelli, Elena, Simula, Francesco, Tosoratto, Laura, Vicini, Piero
We introduce a natively distributed mini-application benchmark representative of plastic spiking neural network simulators. It can be used to measure performances of existing computing platforms and to drive the development of future parallel/distrib
Externí odkaz:
http://arxiv.org/abs/1310.8478
Autor:
Ammendola, Roberto, Bernaschi, Massimo, Biagioni, Andrea, Bisson, Mauro, Fatica, Massimiliano, Frezza, Ottorino, Cicero, Francesca Lo, Lonardo, Alessandro, Mastrostefano, Enrico, Paolucci, Pier Stanislao, Rossetti, Davide, Simula, Francesco, Tosoratto, Laura, Vicini, Piero
Modern GPUs support special protocols to exchange data directly across the PCI Express bus. While these protocols could be used to reduce GPU data transmission times, basically by avoiding staging to host memory, they require specific hardware featur
Externí odkaz:
http://arxiv.org/abs/1307.8276
Autor:
Ammendola, Roberto, Biagioni, Andrea, Frezza, Ottorino, Geurts, Werner, Goossens, Gert, Cicero, Francesca Lo, Lonardo, Alessandro, Paolucci, Pier Stanislao, Rossetti, Davide, Simula, Francesco, Tosoratto, Laura, Vicini, Piero
This is the second of a planned collection of four yearly volumes describing the deployment of a heterogeneous many-core platform for experiments on scalable custom interconnects and management of fault and critical events, applied to many-process ap
Externí odkaz:
http://arxiv.org/abs/1307.1270
Autor:
Ammendola, Roberto, Biagioni, Andrea, Frezza, Ottorino, Cicero, Francesca Lo, Lonardo, Alessandro, Paolucci, Pier Stanislao, Rossetti, Davide, Simula, Francesco, Tosoratto, Laura, Vicini, Piero
Many tile systems require techniques to be applied to increase components resilience and control the FIT (Failures In Time) rate. When scaling to peta- exa-scale systems the FIT rate may become unacceptable due to component numerosity, requiring more
Externí odkaz:
http://arxiv.org/abs/1307.0433
The Distributed Network Processor: a novel off-chip and on-chip interconnection network architecture
Autor:
Biagioni, Andrea, Cicero, Francesca Lo, Lonardo, Alessandro, Paolucci, Pier Stanislao, Perra, Mersia, Rossetti, Davide, Sidore, Carlo, Simula, Francesco, Tosoratto, Laura, Vicini, Piero
One of the most demanding challenges for the designers of parallel computing architectures is to deliver an efficient network infrastructure providing low latency, high bandwidth communications while preserving scalability. Besides off-chip communica
Externí odkaz:
http://arxiv.org/abs/1203.1536
Autor:
Ammendola, Roberto, Biagioni, Andrea, Frezza, Ottorino, Cicero, Francesca Lo, Lonardo, Alessandro, Paolucci, Pier Stanislao, Rossetti, Davide, Salamon, Andrea, Salina, Gaetano, Simula, Francesco, Tosoratto, Laura, Vicini, Piero
We describe herein the APElink+ board, a PCIe interconnect adapter featuring the latest advances in wire speed and interface technology plus hardware support for a RDMA programming model and experimental acceleration of GPU networking; this design al
Externí odkaz:
http://arxiv.org/abs/1102.3796
Autor:
Ammendola, Roberto, Biagioni, Andrea, Frezza, Ottorino, Cicero, Francesca Lo, Lonardo, Alessandro, Paolucci, Pier, Petronzio, Roberto, Rossetti, Davide, Salamon, Andrea, Salina, Gaetano, Simula, Francesco, Tantalo, Nazario, Tosoratto, Laura, Vicini, Piero
Many scientific computations need multi-node parallelism for matching up both space (memory) and time (speed) ever-increasing requirements. The use of GPUs as accelerators introduces yet another level of complexity for the programmer and may potentia
Externí odkaz:
http://arxiv.org/abs/1012.0253