Zobrazeno 1 - 10
of 30
pro vyhledávání: '"TESLENKO, MAXIM"'
Autor:
Teslenko, Maxim, Dubrova, Elena
Redundancy identification is an important step of the design flow that typically follows logic synthesis and optimization. In addition to reducing circuit area, power consumption, and delay, redundancy removal also improves testability. All commercia
Externí odkaz:
http://arxiv.org/abs/1503.06632
Autor:
Teslenko, Maxim, Dubrova, Elena
Dominators provide a general mechanism for identifying reconverging paths in graphs. This is useful for a number of applications in Computer-Aided Design (CAD) including signal probability computation in biased random simulation, switching activity e
Externí odkaz:
http://arxiv.org/abs/1503.04994
Autor:
Teslenko, Maxim
This dissertation is in the area of Computer-Aided Design (CAD) of digital Integrated Circuits (ICs). Today's digital ICs, such as microprocessors, memories, digital signal processors (DSPs), etc., range from a few thousands to billions of logic gate
Externí odkaz:
http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4700
Autor:
Dubrova, Elena, Teslenko, Maxim
This paper addresses the problem of finding cycles in the state transition graphs of synchronous Boolean networks. Synchronous Boolean networks are a class of deterministic finite state machines which are used for the modeling of gene regulatory netw
Externí odkaz:
http://arxiv.org/abs/0901.4448
Autor:
Ronquist, Fredrik, Teslenko, Maxim, van der Mark, Paul, Ayres, Daniel L., Darling, Aaron, Höhna, Sebastian, Larget, Bret, Liu, Liang, Suchard, Marc A., Huelsenbeck, John P.
Publikováno v:
Systematic Biology, 2012 May 01. 61(3), 539-542.
Externí odkaz:
https://www.jstor.org/stable/41515220
For several years, the demand for data has increased. Furthermore, this is a growing trend. There are three ways to meet this demand. One option is to make the network denser; this implies large investments. We can work on improving the bandwidth eff
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::64fdb3ff101b62d696679560527cc087
https://www.econstor.eu/bitstream/10419/101394/1/795034237.pdf
https://www.econstor.eu/bitstream/10419/101394/1/795034237.pdf
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Akademický článek
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Publikováno v:
2010 40th IEEE International Symposium on Multiple-Valued Logic (ISMVL); 2010, p144-149, 6p
Publikováno v:
Proceedings of the Conference: Design, Automation & Test in Europe; 3/10/2008, p1286-1291, 6p