Zobrazeno 1 - 10
of 33
pro vyhledávání: '"T.S. Barnett"'
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 21:337-341
Pre-silicon yield estimators for ASIC products have the potential for improved accuracy based on retrospective critical area and yield analysis of completed designs. A prototype closed-loop system, in which a database of observed yield and computed c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0d56f4a45154456c57d360d1311fbf3a
https://doi.org/10.1109/tsm.2008.2001207
https://doi.org/10.1109/tsm.2008.2001207
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 21:329-336
Today's sophisticated design-for-manufacturability (DFM) methodologies provide a designer with an overwhelming amount of choices, many with significant costs and unclear value. The technology challenges of subwavelength lithography, new materials, de
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::065e1573dcc2c516adf1fee1d99c212a
https://doi.org/10.1109/tsm.2008.2001206
https://doi.org/10.1109/tsm.2008.2001206
Publikováno v:
IEEE Design & Test of Computers. 23:110-116
A key productivity metric in semiconductor manufacturing is wafer test yield - the fraction of dies deemed functional following wafer probe testing. Wafer test yield is directly related to semiconductor manufacturing profitability: The higher the yie
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8e141c0ce8d7c1c484195a7b9dd0cda9
https://doi.org/10.1109/mdt.2006.38
https://doi.org/10.1109/mdt.2006.38
Publikováno v:
IEEE Transactions on Reliability. 52:296-300
The integrated yield-reliability model for integrated circuits allows one to estimate the yield, following both wafer probe and burn-in testing. The model is based on the long observed clustering of defects and the experimentally verified relation be
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::90bdb2619815eccadc9cbf7b6926434e
https://doi.org/10.1109/tr.2003.816418
https://doi.org/10.1109/tr.2003.816418
Publikováno v:
2008 IEEE/SEMI Advanced Semiconductor Manufacturing Conference.
In 65nm and smaller technologies, Vmin fails account for a substantial portion of the total fails seen in memories. Redundancy has traditionally been used to fix random point defects which can be modeled with Critical Area Analysis. As technologies m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::49e5f7b26878af794b2dc6fc4df87c87
https://doi.org/10.1109/asmc.2008.4529077
https://doi.org/10.1109/asmc.2008.4529077
Autor:
T.S. Barnett, Adit D. Singh
Publikováno v:
System-on-Chip: Next Generation Electronics ISBN: 9780863415524
This chapter has presented a unified approach to yield and reliability modelling. Fundamentally, the successful integration of yield and early-life reliability results from the fact that latent early-life reliability defects, while smaller and placed
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d9ad4389aa0f9ca531552f06a4c823f1
https://doi.org/10.1049/pbcs018e_ch25
https://doi.org/10.1049/pbcs018e_ch25
Publikováno v:
VTS
An integrated yield-reliability model is verified using burn-in data from 77,000 microprocessor units manufactured by IBM Microelectronics. The model is based on the fact that defects over semiconductor wafers are not randomly distributed, but have a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0b900c2b0a7b9e1b9a5bf066bc707082
https://doi.org/10.1109/vts.2002.1011114
https://doi.org/10.1109/vts.2002.1011114
Publikováno v:
ITC
This paper validates an integrated yield-reliability model for redundant memory using yield and stress test data from a 36 Mbit SRAM memory chip and an 8 Mbit embedded DRAM chip. In both cases, those chips determined functional following wafer test a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::014742b478180f7601eb37147763a1f7
https://doi.org/10.1109/test.2002.1041821
https://doi.org/10.1109/test.2002.1041821
Publikováno v:
VTS
Defects have long been known to cluster on semiconductor wafers. Recent research has shown that this fact may be exploited to produce die of high reliability, (i.e. decreased infant mortality), by sorting die into bins based on how many of their neig
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3b160aad8da81e8133e96c79029a41d3
https://doi.org/10.1109/vts.2001.923457
https://doi.org/10.1109/vts.2001.923457