Zobrazeno 1 - 10
of 93
pro vyhledávání: '"T.J. Yamaguchi"'
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 23:997-1009
This paper presents the application of a new analytic signal method for measuring several different kinds of clock skew in the clock distribution network of microprocessors. First, key terms are defined, and other existing skew measurement methods ar
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::56b099b478154d14fa11b1c3cfc06e86
https://doi.org/10.1109/tcad.2004.829814
https://doi.org/10.1109/tcad.2004.829814
Publikováno v:
IEEE Transactions on Computers. 51:486-497
The overall throughput of automatic test equipment (ATE) is affected by the download time of test data. An effective approach to the reduction of the download time is to compress test data before the download. A compression algorithm for test data sh
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8edfd720a5bdef3d6a73e878355ca0ce
https://doi.org/10.1109/tc.2002.1004588
https://doi.org/10.1109/tc.2002.1004588
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 8:594-605
The focus of high-level built-in self-test (BIST) synthesis is register assignment, which involves system register assignment, BIST register assignment, and interconnection assignment. To reduce the complexity involved in the assignment process, exis
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::64b9e8416913c1b14e61df30646c9140
https://doi.org/10.1109/92.894164
https://doi.org/10.1109/92.894164
Autor:
M. Ishida, T.J. Yamaguchi
Publikováno v:
ATS
Total jitter measurement has been ready to perform jitter testing of HSIO integrated SoCs in an HV production testing environment. Since it requires no special loadboard nor additional hardware or instrumentation, it provides a cost-effective total j
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e201cce0e1a3f9c2b76b0cec031a6491
https://doi.org/10.1109/ats.2008.38
https://doi.org/10.1109/ats.2008.38
Publikováno v:
ITC
This paper proposes an FFT-based method that separates random jitter from deterministic jitter in clock and data patterns, with a 10X reduction in test time. The method has been verified experimentally on a 2.5 Gbps clock pattern & 7-stage PRBS, and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b7671c4c5f83bd669cd900ec395df371
https://doi.org/10.1109/test.2007.4437607
https://doi.org/10.1109/test.2007.4437607
Publikováno v:
ITC
This paper introduces a new method for measuring jitter in GHz signals using ATE. The wideband DeltaPhi method employs a frequency-shifting approach and has been verified experimentally to at least 2.5 GHz
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0d87c2d1d088666c6e57780154cf4382
https://doi.org/10.1109/test.2005.1583980
https://doi.org/10.1109/test.2005.1583980
Akademický článek
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Akademický článek
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Autor:
T.J. Yamaguchi
Publikováno v:
2004 International Conferce on Test.
For the verification of high-speed serial I/O devices, a new architecture, which is different from the conventional ET sampling method, must be developed to measure ultra-wideband jitter in the bit stream transmitted from a multi-Gb/s physical layer
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::28c6b3dc381cdc5830dd71baec7c1062
https://doi.org/10.1109/test.2004.1387442
https://doi.org/10.1109/test.2004.1387442
Publikováno v:
ITC
This paper presents a new jitter tolerance model that includes the effect of deterministic jitter in interconnects. First, it is shown by experiment that the deterministic jitter in a cable can significantly affect its jitter tolerance. Then, the new
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2cf99803fe6a41e40072e1dfe03faee9
https://doi.org/10.1109/test.2003.1270825
https://doi.org/10.1109/test.2003.1270825