Výsledky vyhledávání

A low-power RISC microprocessor using dual PLLs in a 0.13 μm SOI technology with copper interconnect and low-k BEOL dielectric

Autor: Erwin B. Cohen, Jeffrey S. Zimmerman, P. McCormick, Paul D. Kartschoke, S. Charlebois, Peter A. Sandon, B. Singer, S. Geissler, Norman J. Rohrer, David Appenzeller, T. von Reyn, Gerard M. Salem

Publikováno v: 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

Microprocessors achieving clock frequencies >1 GHz for mobile applications require solutions to maintain long battery life. Circuit and architecture solutions for dynamic frequency switching between multiple PLLs, DC power reduction methods, and impa

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::17620c55d20225d0fac0be28c0461bbf
https://doi.org/10.1109/isscc.2002.992979

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A 1 MB, 100 MHz integrated L2 cache memory with 128b interface and ECC protection

Autor: Glenn Peter Giacalone, S. Divakaruni, Peter Joel Jenkins, John A. Fifield, M. Hodges, Jeffrey S. Zimmerman, Robert E. Busch, A. Davidovich, M. Vincent, M. Kozyrczak, Christopher P. Miller, Wayne J. Howell, C. Reed, F. Creed, Thomas E. Obremski, Charles Edward Drake, T. von Reyn, G. Rohrbaugh, C. Ematrudo

Publikováno v: 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

Several cache-DRAMs have been reported, but all require multiple chips to implement an L2 cache system. The advent of 20 ns, 16 Mb DRAM technology has made a high-speed single-chip 1MB cache possible, replacing multiple SRAM and logic modules, saving

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::dc4f3df86c68ee4b283ada19fb890d82
https://doi.org/10.1109/isscc.1996.488721

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